Patents by Inventor Joel Kanyandekwe

Joel Kanyandekwe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11854805
    Abstract: A method for forming SiGe-based regions with different Ge concentrations is provided. After defining the regions 1, 2 on a SOI substrate, a grating of masking patterns is formed on at least one region 2. After the epitaxial growth of a Ge-based layer in each of the regions, a first vertical diffusion is carried out. A second horizontal diffusion is then carried out such that the Ge diffuses beneath the masking patterns of the region 2. Thus, the region 2 has a Ge concentration that is lower than the Ge concentration of the region 1.
    Type: Grant
    Filed: January 26, 2022
    Date of Patent: December 26, 2023
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Joël Kanyandekwe, Cyrille Le Royer
  • Publication number: 20220384573
    Abstract: A method for manufacturing a pFET transistor, the method for manufacturing the transistor including providing a base structure comprising a silicon channel and a gate structure, the gate structure surrounding the channel leaving two flanks of the channel free; growing a first layer made from silicon-germanium alloy on the flanks of the channel; enriching the channel with germanium atoms from the first layer; and forming a drain region and a source region on either side of the channel.
    Type: Application
    Filed: May 27, 2022
    Publication date: December 1, 2022
    Inventors: Cyrille LE ROYER, Joël KANYANDEKWE, Sylvain BARRAUD
  • Publication number: 20220310394
    Abstract: A method for forming crystalline SiC-based regions on either side of an N-type transistor channel, including: providing a substrate including a silicon-based layer having a thickness e, forming at least one masking pattern on the silicon-based layer, with the at least one masking pattern having openings, with the openings corresponding to implantation regions of the silicon-based layer, amorphising the silicon-based layer through the openings of the at least one masking pattern, in the implantation regions, to a depth d strictly less than the thickness e, so as to form amorphised implantation regions in the silicon-based layer, implanting carbon into amorphous implantation regions, performing thermal recrystallisation annealing to turn the amorphised implantation regions into crystalline SiC-based regions, the method including: after forming the crystalline SiC-based regions, forming a transistor gate on the silicon-based layer, directly at the edge of the crystalline SiC-based regions.
    Type: Application
    Filed: March 24, 2022
    Publication date: September 29, 2022
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Joël KANYANDEKWE, Cyrille LE ROYER
  • Publication number: 20220238338
    Abstract: A method for forming SiGe-based regions with different Ge concentrations is provided. After defining the regions 1, 2 on a SOI substrate, a grating of masking patterns is formed on at least one region 2. After the epitaxial growth of a Ge-based layer in each of the regions, a first vertical diffusion is carried out. A second horizontal diffusion is then carried out such that the Ge diffuses beneath the masking patterns of the region 2. Thus, the region 2 has a Ge concentration that is lower than the Ge concentration of the region 1.
    Type: Application
    Filed: January 26, 2022
    Publication date: July 28, 2022
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Joël KANYANDEKWE, Cyrille LE ROYER
  • Patent number: 9679972
    Abstract: A semiconductor structure can include a substrate and a substrate layer. The substrate can be formed of silicon and the substrate layer can be formed of silicon germanium. Above the substrate and under the substrate layer there can be provided a multilayer substructure. The multilayer substructure can include a first layer and a second layer. The first layer can be formed of a first material and the second layer can be formed of second material. A method can include forming a multilayer substructure on a substrate, annealing the multilayer substructure, and forming a substrate layer on the multilayer substructure.
    Type: Grant
    Filed: April 20, 2016
    Date of Patent: June 13, 2017
    Assignees: GLOBALFOUNDRIES Inc., International Business Machines Corporation, STMicroelectronics, Inc.
    Inventors: Jody Fronheiser, Murat Kerem Akarvardar, Stephen Bedell, Joel Kanyandekwe