Abstract: At least one silicon wafer is loaded into a closed vessel that contains a first solution that includes ammonium hydroxide, hydrogen peroxide and DI water. This acidic solution is removed from the vessel and DI water is introduced into the vessel until wafers are completely immersed. The DI water is then removed from the vessel and a second solution that includes hydrofluoric acid, hydrochloric acid solution and DI water is added to the vessel to fully immerse the wafer. The second solution is then removed from the vessel, and as the second solution is being drained from the vessel, an alcohol solution in a hot and low-pressure nitrogen carrier gas is introduced to the vessel, such that as the level of the liquid within the vessel falls below the height of the wafer within the vessel, the surface of the wafer is dried due to surface tension. The thin coating of alcohol solvent on the wafer ensures that the surface of the wafer is hydrogen terminated, thus hydrophobic.

Abstract: A voltage controlled oscillator includes a varactor (201) and a transistor (202) and a ground via (203), of epitaxially grown silicon that is etched to provide respective pedestals embodying the varactor (201) and the transistor (202) and the ground via (203), an L-C resonator circuit, the varactor (201) and an inductor providing a tank circuit that changes the frequency of the L-C resonator circuit, and that shifts the average frequency of the oscillator to that of an input voltage to the collector of the transistor (202).

Abstract: It has been identified that a known loss mechanism in the access path to a mesa type device is more significant than previously believed. The source of the loss is due to the electromagnetic interaction of the wire bond and the device side wall which induces an image current at the side wall along the path of the wire bond. According to the teachings of the present invention, a process for forming a conductive coating on a semiconductor device is disclosed. The coating reduces high frequency losses associated with the device. The processes disclosed are compatible with existing semiconductor fabrication devices and advantageously provide improved uniformity and repeatability.

Abstract: A mesa-type PIN diode and method for making same are disclosed. A diode made according to the present invention includes a junction formed in the top surface of the mesa-shaped structure, having an area that is less than (and preferrably, approximately half) the area of the top surface. A highly-doped, N-type conducting layer is formed in the side-walls of the mesa-shaped structure. The resulting diode is subject to greatly reduced charge carrier recombination effects and suffers from much less carrier-to-carrier scattering than conventional diodes. Thus, a diode made according to the present invention is capable of achieving much higher stored charge, lower resistance, lower capacitance, better switching characteristics, and lower power consumption than one made according to the prior art. Particular utility is found, inter alia, in the areas of high-frequency microwave and monolithic circuits.

Abstract: A mesa-type PIN diode and method for making same are disclosed. A diode made according to the present invention includes a junction formed in the top surface of the mesa-shaped structure, having an area that is less than (and preferrably, approximately half) the area of the top surface. A highly-doped, N-type conducting layer is formed in the side-walls of the mesa-shaped structure. The resulting diode is subject to greatly reduced charge carrier recombination effects and suffers from much less carrier-to-carrier scattering than conventional diodes. Thus, a diode made according to the present invention is capable of achieving much higher stored charge, lower resistance, lower capacitance, better switching characteristics, and lower power consumption than one made according to the prior art. Particular utility is found, inter alia, in the areas of high-frequency microwave and monolithic circuits.

Abstract: A semiconductor device and associated method of fabrication in which the device includes a semiconductor substrate having a cavity therein extending in a frame pattern. An insulating layer such as one of silicon nitride is deposited in the cavity followed by the deposition of polysilicon to substantially fill the cavity and provide structural support. An epitaxy layer is formed over the surface of the substrate along with a second insulating layer having windows defined therein for enabling ohmic contact with the epitaxy layer and substrate, resectively. Metallization is deposited to form separate beam leads to provide ohmic contact at the epitaxy layer and substrate.

Abstract: A semiconductor device and associated method of fabrication in which the device includes a semiconductor substrate having a cavity therein extending in a frame pattern. An insulating layer such as one of silicon nitride is deposited in the cavity followed by the deposition of polysilicon to substantially fill the cavity and provide structural support. An epitaxy layer is formed over the surface of the substrate along with a second insulating layer having windows defined therein for enabling ohmic contact with the epitaxy layer and substrate, respectively. Metallization is deposited to form separate beam leads to provide ohmic contact at the epitaxy layer and substrate.

Abstract: A process for the fabrication of semiconductor components and in particular a process in which the components are fabricated with a controlled spacing of etched channels. The process is in particular utilized in fabricating a monolithic array of elements such as a pin diode array. The process of the present invention combines the use of an anisotropic silicon etching process for the desired device geometries with a means of defining all device surface topology by substantially a single photomask thus eliminating critical mask alignment. A second embodiment of the invention is also described employing fewer layers of deposition with a double photomask step.

Abstract: The invention contemplates a method of making a solar-cell construction wherein plural spaced elongate unit cells of an array are formed from a parallel-grooved single wafer of substrate material of a first conductivity type, with adjacent sidewalls of adjacent units at each inter-unit groove formation. In the transverse succession of such groove formations, the sidewalls of every other groove are formed with regions of a second conductivity type, so that at or near the radiation-exposure surface of each unit there is but one junction between first and second conductivity types. In one general form, all grooves go all the way between upper and lower wafer surfaces, thus defining discrete single-cell units; in another general form, every other groove ends close to but short of the upper surface, thus defining discrete twin-cell units. The units are series-connected by making ohmic connection between the second conductivity-type region of one unit and a first conductivity-type region of an adjacent unit.

Abstract: The invention contemplates a solar-cell construction wherein plural spaced elongate unit cells of an array are formed from a parallel-grooved single wafer of substrate material of a first conductivity type, with adjacent sidewalls of adjacent units at each inter-unit groove formation. In the transverse succession of such groove formations, the sidewalls of every other groove are formed with regions of a second conductivity type, so that at or near the radiation-exposure surface of each unit there is but one junction between first and second conductivity types. In one general form, all grooves go all the way between upper and lower wafer surfaces, thus defining discrete single-cell units; in another general form, every other groove ends close to but short of the upper surface, thus defining discrete twin-cell units. The units are series-connected by making ohmic connection between the second conductivity-type region of one unit and a first conductivity-type region of an adjacent unit.

Abstract: The invention contemplates a solar-cell construction wherein plural spaced elongate unit cells of an array are formed from a parallel-grooved single wafer of substrate material of a first conductivity type, with adjacent sidewalls of adjacent units at each inter-unit groove formation. In the transverse succession of such groove formations, the sidewalls of every other groove are formed with regions of a second conductivity type, so that at or near the radiation-exposure surface of each unit there is but one junction between first and second conductivity types. In one general form, all grooves go all the way between upper and lower wafer surfaces, thus defining discrete single-cell units; in another general form, every other groove ends close to but short of the upper surface, thus defining discrete twin-cell units. The units are series-connected by making ohmic connection between the second conductivity-type region of one unit and a first conductivity-type region of an adjacent unit.