Abstract: An example computing resource may include computing circuitry that includes logic. The logic may be executable to receive a series of data and an end of transfer message associated with the series of data. The logic may also be executable to, in response to a determination that the end of transfer message indicates a request for acknowledgment, send an acknowledgment to a sender of the series of data after receipt of all the series of data at the computing circuitry is complete and before the series of data is committed to a memory associated with a processing resource. The memory and the processing resource are separate from the computing circuitry. The logic may also be executable to, in response to a request to commit received data, commit the acknowledged and uncommitted series of data to the memory associated with the processing resource and interrupt the processing resource. The interrupt indicates that the acknowledged series of data is committed to the memory associated with the processing resource.

Abstract: An embodiment of the invention is a processor comprising a direct execution parser configured to control the processing of digital data by semantically parsing data; a plurality of semantic processing units configured to perform data operations when prompted by the direct execution parser; and a plurality of output buffers for buffering data received from the plurality of semantic processing units. Another embodiment of the invention is an interface circuit comprising a packer circuit for receiving data from a semantic processing unit and a plurality of buffers for receiving the data. The interface circuit unloads the data received to an interface.