Patents by Inventor Joel Landry
Joel Landry has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11953959Abstract: A hybrid apparatus for charging electric vehicles and mining cryptocurrency is provided. The apparatus may comprise an electric power input associated with a rated maximum power capacity, an electric vehicle charger, a cryptocurrency miner and a power coordinator. The electric vehicle charger may have at least one vehicle power outlet and a maximum charger power draw from the electric power input. The cryptocurrency miner may have multiple cryptocurrency mining computers and a maximum miner power draw from the electric power input. Each mining computer may have an adjustable intensity level. The power coordinator may be configured to determine mining power availability within the rated maximum power capacity after prioritizing power demand by the electric vehicle charger, and to direct the cryptocurrency miner to continue mining cryptocurrency by adjusting the intensity levels of the mining computers such that the cryptocurrency miner consumes not more than the mining power availability.Type: GrantFiled: August 9, 2023Date of Patent: April 9, 2024Assignee: Hestia Heating IncorporatedInventors: Joel Landry, Christopher Wayne Searle, Robert Walter Burton, Curtis John Doran
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Patent number: 11638364Abstract: A cryptocurrency mining furnace is provided. The cryptocurrency mining furnace comprises a furnace housing having an air flow path extending from a housing air inlet downstream to a housing air outlet; and at least three separate mining computers. Each mining computer is positioned in the furnace housing in the air flow path upstream of the housing air outlet and includes at least one cryptocurrency mining board. The cryptocurrency mining furnace also comprises a transformer positioned in the furnace housing upstream of the mining computers and downstream of the housing air inlet, the transformer electrically connected to each of the mining computers to power each of the mining computers; and a principal fan positioned in the furnace housing in the air flow path downstream of the transformer and upstream of the mining computers to induce air flow along the air flow path through the transformer and each of the mining computers.Type: GrantFiled: September 28, 2022Date of Patent: April 25, 2023Inventor: Joel Landry
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Patent number: 10936286Abstract: A logic cell for a programmable logic integrated circuit having K function inputs, where K is the largest number such that the logic cell can compute any function of K inputs, and where the logic cell is configurable to implement one bit of a counter in parallel with any independent function of K-1 of the K inputs.Type: GrantFiled: January 8, 2019Date of Patent: March 2, 2021Assignee: Microsemi SoC Corp.Inventors: Jonathan W. Greene, Joel Landry
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Publication number: 20200150925Abstract: A logic cell for a programmable logic integrated circuit having K function inputs, where K is the largest number such that the logic cell can compute any function of K inputs, and where the logic cell is configurable to implement one bit of a counter in parallel with any independent function of K-1 of the K inputs.Type: ApplicationFiled: January 8, 2019Publication date: May 14, 2020Applicant: Microsemi SoC Corp.Inventors: Jonathan W. Greene, Joel Landry
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Patent number: 10020811Abstract: A random access memory circuit adapted for use in a field programmable gate array integrated circuit device is disclosed. The FPGA has a programmable array with logic modules and routing interconnects programmably coupleable to the logic modules and the RAM circuit. The RAM circuit has three ports: a first readable port, a second readable port, and a writeable port. The read ports may be programmably synchronous or asynchronous and have a programmably bypassable output pipeline register. The RAM circuit is especially well adapted for implementing register files. A novel interconnect method is also described.Type: GrantFiled: September 25, 2017Date of Patent: July 10, 2018Assignee: Microsemi SoC Corp.Inventors: Joel Landry, Jonathan Greene, William C. Plants, Wenyi Feng
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Publication number: 20180026641Abstract: A random access memory circuit adapted for use in a field programmable gate array integrated circuit device is disclosed. The FPGA has a programmable array with logic modules and routing interconnects programmably coupleable to the logic modules and the RAM circuit. The RAM circuit has three ports: a first readable port, a second readable port, and a writeable port. The read ports may be programmably synchronous or asynchronous and have a programmably bypassable output pipeline register. The RAM circuit is especially well adapted for implementing register files. A novel interconnect method is also described.Type: ApplicationFiled: September 25, 2017Publication date: January 25, 2018Inventors: Joel Landry, Jonathan Greene, William C. Plants, Wenyi Feng
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Patent number: 9780792Abstract: A random access memory circuit adapted for use in a field programmable gate array integrated circuit device is disclosed. The FPGA has a programmable array with logic modules and routing interconnects programmably coupleable to the logic modules and the RAM circuit. The RAM circuit has three ports: a first readable port, a second readable port, and a writeable port. The read ports may be programmably synchronous or asynchronous and have a programmably bypassable output pipeline register. The RAM circuit is especially well adapted for implementing register files. A novel interconnect method is also described.Type: GrantFiled: May 21, 2013Date of Patent: October 3, 2017Assignee: MICROSEMI SOC CORP.Inventors: Joel Landry, Jonathan Greene, William C. Plants, Wenyi Feng
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Publication number: 20130271180Abstract: A random access memory circuit adapted for use in a field programmable gate array integrated circuit device is disclosed. The FPGA has a programmable array with logic modules and routing interconnects programmably coupleable to the logic modules and the RAM circuit. The RAM circuit has three ports: a first readable port, a second readable port, and a writeable port. The read ports may be programmably synchronous or asynchronous and have a programmably bypassable output pipeline register. The RAM circuit is especially well adapted for implementing register files. A novel interconnect method is also described.Type: ApplicationFiled: May 21, 2013Publication date: October 17, 2013Inventors: Joel Landry, Jonathan Greene, William C. Plants, Wenyi Feng
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Patent number: 8468328Abstract: System and method for verifying compatibility of computer equipment with a software product. A system and method are provided to verify compatibility of computer equipment with software. This verification can include gathering information about configurations of the computer equipment, and creating at least one file based on the information. The file or files coordinate testing of the computer equipment. The testing produces results that can be stored and analyzed or evaluated. The results can be contained in a file or a plurality of files. The results provide a description of the configurations in addition to an indication of whether the testing has produced any failures. The configuration descriptions or parts thereof can be stored in a configuration database that can be used to apply credit against future testing of computer equipment so that future testing needs can be reduced.Type: GrantFiled: December 2, 2009Date of Patent: June 18, 2013Assignee: Red Hat, Inc.Inventors: Lawrence Edward Troan, Robin Joel Landry, David Keith Lawrence, Willard Gordon Woods
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Patent number: 8446170Abstract: A random access memory circuit adapted for use in a field programmable gate array integrated circuit device is disclosed. The FPGA has a programmable array with logic modules and routing interconnects programmably coupleable to the logic modules and the RAM circuit. The RAM circuit has three ports: a first readable port, a second readable port, and a writeable port. The read ports may be programmably synchronous or asynchronous and have a programmably bypassable output pipeline register. The RAM circuit is especially well adapted for implementing register files. A novel interconnect method is also described.Type: GrantFiled: May 3, 2012Date of Patent: May 21, 2013Assignee: Actel CorporationInventors: Joel Landry, Jonathan Greene, William C. Plants, Wenyi Feng
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Publication number: 20120280711Abstract: A random access memory circuit adapted for use in a field programmable gate array integrated circuit device is disclosed. The FPGA has a programmable array with logic modules and routing interconnects programmably coupleable to the logic modules and the RAM circuit. The RAM circuit has three ports: a first readable port, a second readable port, and a writeable port. The read ports may be programmably synchronous or asynchronous and have a programmably bypassable output pipeline register. The RAM circuit is especially well adapted for implementing register files. A novel interconnect method is also described.Type: ApplicationFiled: May 3, 2012Publication date: November 8, 2012Inventors: Joel Landry, Jonathan Greene, William C. Plants, Wenyi Feng
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Patent number: 8067959Abstract: A delay line compensated for process, voltage, and temperature variations, includes a delay locked loop (DLL) configured to delay a digital signal by the clock period of the digital signal, the DLL including a DLL delay line arranged as a plurality of cascaded sub-delay lines each sub-delay line providing one of a plurality of delay quanta in response to a digital control signal. A fractionating circuit is configured to generate a digital delay line control signal that is a fraction of the digital control signal. A digital delay line is arranged as a plurality of cascaded sub-delay lines each sub-delay line providing one of a plurality of delay quanta in response to the digital delay line control signal.Type: GrantFiled: March 3, 2010Date of Patent: November 29, 2011Assignee: Actel CorporationInventors: William C. Plants, Suhail Zain, Joel Landry, Gregory W. Bakker, Tomek P. Jasinoski
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Patent number: 7924051Abstract: A computer program product in a computer-readable medium for use in a microcontroller-based control system in a programmable logic integrated circuit device. The computer program product comprises first instructions for initializing the device, second instructions for reading programming data from a data source external to the programmable logic integrated circuit device, third instructions for transferring the programming data into control elements internal to the device. Provision is made for fourth instructions for saving a part of the internal logic state of the user logic programmed into the device into a non-volatile memory block and for fifth instructions for restoring a part of the internal logic state of the user logic programmed into the device from a non-volatile memory block. The device comprises a microcontroller block and a programmable logic block with programming circuitry, and has a sub-bus which couples the microcontroller block to the programming circuitry.Type: GrantFiled: February 5, 2010Date of Patent: April 12, 2011Assignee: Actel CorporationInventors: Gregory Bakker, Joel Landry, William C. Plants
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Patent number: 7913081Abstract: Embodiments of the present invention provide methods and systems for dynamically certifying components. Various entities may participate in the certification process. Operational data from live systems in use may also be collected and considered as part of the certification for a component. This information is then gathered into a database, which may be shared or made publicly available over a network, such as the Internet. In addition, in some embodiments, a proposed system may be certified. A proposed configuration may be submitted to a certification service. The certification service may then analyze the proposed system and determine whether there is a sufficient data to certify the proposed system.Type: GrantFiled: June 9, 2005Date of Patent: March 22, 2011Assignee: Red Hat, Inc.Inventors: Richard Ding Li, Robin Joel Landry
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Patent number: 7885122Abstract: A flash-based programmable integrated circuit includes programmable circuitry, a flash memory array coupled to the programmable circuitry for configuring it, flash programming circuitry for programming the flash memory array, and an on-chip intelligence, such as a microcontroller or state machine, coupled to the programming circuitry to program the flash memory from off-chip data supplied via an I/O pad, or to refresh the data stored in the flash memory to prevent it from degrading.Type: GrantFiled: September 29, 2009Date of Patent: February 8, 2011Assignee: Actel CorporationInventors: Joel Landry, William C. Plants, Randall Sexton
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Publication number: 20100156459Abstract: A delay line compensated for process, voltage, and temperature variations, includes a delay locked loop (DLL) configured to delay a digital signal by the clock period of the digital signal, the DLL including a DLL delay line arranged as a plurality of cascaded sub-delay lines each sub-delay line providing one of a plurality of delay quanta in response to a digital control signal. A fractionating circuit is configured to generate a digital delay line control signal that is a fraction of the digital control signal. A digital delay line is arranged as a plurality of cascaded sub-delay lines each sub-delay line providing one of a plurality of delay quanta in response to the digital delay line control signal.Type: ApplicationFiled: March 3, 2010Publication date: June 24, 2010Inventors: William C. Plants, Suhail Zain, Joel Landry, Gregory W. Bakker, Tomek P. Jasionowski
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Publication number: 20100134142Abstract: A computer program product in a computer-readable medium for use in a microcontroller-based control system in a programmable logic integrated circuit device. The computer program product comprises first instructions for initializing the device, second instructions for reading programming data from a data source external to the programmable logic integrated circuit device, third instructions for transferring the programming data into control elements internal to the device. Provision is made for fourth instructions for saving a part of the internal logic state of the user logic programmed into the device into a non-volatile memory block and for fifth instructions for restoring a part of the internal logic state of the user logic programmed into the device from a non-volatile memory block. The device comprises a microcontroller block and a programmable logic block with programming circuitry, and has a sub-bus which couples the microcontroller block to the programming circuitry.Type: ApplicationFiled: February 5, 2010Publication date: June 3, 2010Inventors: Gregory Bakker, Joel Landry, William C. Plants
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Publication number: 20100100772Abstract: System and method for verifying compatibility of computer equipment with a software product. A system and method are provided to verify compatibility of computer equipment with software. This verification can include gathering information about configurations of the computer equipment, and creating at least one file based on the information. The file or files coordinate testing of the computer equipment. The testing produces results that can be stored and analyzed or evaluated. The results can be contained in a file or a plurality of files. The results provide a description of the configurations in addition to an indication of whether the testing has produced any failures. The configuration descriptions or parts thereof can be stored in a configuration database that can be used to apply credit against future testing of computer equipment so that future testing needs can be reduced.Type: ApplicationFiled: December 2, 2009Publication date: April 22, 2010Applicant: RED HAT, INC.Inventors: Lawrence Edward Troan, Robin Joel Landry, David Keith Lawrence, Willard Gordon Woods
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Patent number: 7701246Abstract: A delay line compensated for process, voltage, and temperature variations, includes a delay locked loop (DLL) configured to delay a digital signal by the clock period of the digital signal, the DLL including a DLL delay line arranged as a plurality of cascaded sub-delay lines each sub-delay line providing one of a plurality of delay quanta in response to a digital control signal. A fractionating circuit is configured to generate a digital delay line control signal that is a fraction of the digital control signal. A digital delay line is arranged as a plurality of cascaded sub-delay lines each sub-delay line providing one of a plurality of delay quanta in response to the digital delay line control signal.Type: GrantFiled: July 17, 2008Date of Patent: April 20, 2010Assignee: Actel CorporationInventors: William C. Plants, Suhail Zain, Joel Landry, Gregory W. Bakker, Tomek Jasionowski
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Patent number: 7683660Abstract: A computer program product in a computer-readable medium for use in a microcontroller-based control system in a programmable logic integrated circuit device is disclosed. The computer program product comprises first instructions for initializing the device, second instructions for reading programming data from a data source external to the programmable logic integrated circuit device, third instructions for transferring the programming data into control elements internal to the programmable logic integrated circuit device. Provision is made for fourth instructions for saving at least a part of the internal logic state of the user logic programmed into the programmable logic integrated circuit device into a non-volatile memory block and for fifth instructions for restoring at least a part of the internal logic state of the user logic programmed into the programmable logic integrated circuit device from a non-volatile memory block.Type: GrantFiled: January 31, 2008Date of Patent: March 23, 2010Assignee: Actel CorporationInventors: Gregory Bakker, Joel Landry, William C. Plants