Abstract: A system for synchronizing a clock includes a phase-locked loop (PLL) circuit that generates or receives (304) timing errors that are based on timing information from multiple timing sources. Gain blocks (214) weight (306) the timing errors, which are then combined (308) into a loop time error. A loop integrator (226) integrates (310) the loop time error to produce an input used to adjust (312) an oscillator frequency. A corresponding oscillator clock signal is fed back (240) to one or more phase detectors (206), which receive (302) timing reference signals and generate timing errors. When a timing errors indicates that a problem exists with a timing source, the impact of the problematic timing source is reduced (430, 504), or oscillator frequency adjustments are suspended (608). When used on a satellite (700), at least one of the timing errors can be based on times of transmit and times of arrival of time messages exchanged between the satellite and its neighbors (716).

Abstract: A method and apparatus are provided for operating a phased-array antenna (14) on a satellite-based communications node (10) in more than one mode by controlling the number of beam-forming elements and by applying appropriate phase-control and/or amplitude-control coefficients to the selected elements. The antenna can be operated as a diffused-beam antenna at a relatively low data rate, enabling the satellite-communications node (10) to communicate with a first terrestrial communications node (22). The antenna can also be operated to generate multiple focused-beam antenna patterns each communicating at a relatively high data rate, enabling the satellite-communications node (10) to communicate with a different terrestrial communications node (20) by changing the amplitude and/or the phase coefficients as well as the number of beam-forming elements.

Abstract: A system for switching radio frequency signals from an input side (5, FIG. 1 ) to an output side (6) can be used to combine multiple input signals to form a single output and to distribute a single input signal to form multiple outputs. Gain correction amplifiers (20, 25) are employed to adjust the overall gain of a particular column and row of the switch matrix which minimizes the effect of variations in the gain of the amplified switching elements (30) which perform the switching function. Resistive matching units (70, FIG. 2) provide coupling to and from the amplified switching elements (30) without substantially changing the characteristic impedance of the input and output paths.

Abstract: In a satellite communication system, a satellite (FIG. 1, 150) determines its position through the reception of global positioning system signals (180). The satellite (150) then broadcasts its position by way of a wide coverage antenna (152) transmitting a low data rate position broadcast (125). A ground station (110) receives the low data rate position broadcast (125) and directs a narrow beam antenna (120) to the reported position of the satellite (150). The ground station (110) then begins high data rate communications with the satellite (150) through the narrow beam antenna (120).

Abstract: An apparatus (10) and method (100) optimize the transmit output power of a power amplifier (14) while providing for controlled backoff independent of temperature, gain stackup or other common error effects. The apparatus (10) and method (100) are particularly relevant to single channel per carrier (SCPC) satellite transmissions, such as a K-band satellite transmissions. The apparatus (10) and method (100) provide the ability to set a maximum drive level of a power amplifier (14) using a feedback loop without overdriving the power amplifier (14) into compression. This approach controls the spectral regrowth that results from running the power amplifier (14) in saturation and limits the AM/PM conversion in the power amplifier (14).

Abstract: An apparatus and accompanying method for demodulating with baseband Doppler frequency shift compensation. An RF section (20) down-converts received data communication signals (12) to baseband. A/D converters (24, 26) digitize I, Q quadrature baseband signal components. Phase (32) and frequency (50) tracking loops reside on a common digital ASIC substrate (28). A complex multiplier (30) rotates digitized baseband signals by a digitized oscillation signal, producing Doppler shift compensated signals. The phase tracking loop (32) estimates data and generates a pure phase error signal from which data modulation and Doppler shift compensation influences have been removed, which drives a frequency discriminator (52) that identifies either clockwise or counterclockwise phase rotation for each symbol (18). An integrator (54) combines identification results over a burst and a numerically controlled oscillator (56) adjusts the digitized oscillation signal frequency in a constant frequency step.