Abstract: A signal processing circuit includes a circuit stage for operating on signals in a signal path of an input signal, including main circuitry for operating on relatively small-value signals and alternative circuitry for amplifying/processing signals during a condition which otherwise would cause thermal imbalance in the main circuitry. The circuit stage includes switching circuitry for coupling signals in the signal path of the input signal to the main input circuitry during normal small-signal operating conditions and for coupling signals in the signal path of the input signal to the alternative circuitry during the condition which otherwise would cause thermal imbalance in the main circuitry.

Abstract: An amplifier includes a differential amplifier (10) having an input stage (20) for amplifying a differential input signal (Vin), and an output stage (6) coupled to the input stage (20) for producing and output signal (Vout). The input stage (20) includes main input circuitry (20A) for amplifying small-signal values of the input signal (Vin) and alternative input circuitry (20B) for amplifying the input signal (Vin) during conditions which cause thermal imbalance in the main input circuitry (20B). The input stage (20) includes switching circuitry (12) for coupling the input signal (Vin) to the main input circuitry (20A) during normal small-signal operating conditions and to the alternative input circuitry (20A) during large-signal operating conditions that cause thermal imbalance in the main input circuitry (20B).

Abstract: A low power current feedback amplifier having a lower output impedance input stage is provided. To reduce the output impedance, an input stage comprises a closed-loop input buffer. An exemplary input buffer comprises a closed-loop current feedback amplifier configured within the overall current feedback amplifier, wherein the output of the input buffer corresponds to the inverting node of the overall current feedback amplifier. The closed-loop configuration of the input buffer is facilitated by the use of an internal feedback resistor coupled from an inverting input terminal of the input buffer to the output of the input buffer, which corresponds to the inverting input terminal of the overall current feedback amplifier. The closed-loop input buffer realizes a low output impedance since the loop gain reduces the output impedance of the input buffer. With a lower output impedance, the bandwidth of the current feedback amplifier becomes more independent of the gain, even at low current implementations.

Abstract: A low power current feedback amplifier having a lower output impedance input stage is provided. To reduce the output impedance, an input stage comprises a closed-loop input buffer. An exemplary input buffer comprises a closed-loop current feedback amplifier configured within the overall current feedback amplifier, wherein the output of the input buffer corresponds to the inverting node of the overall current feedback amplifier. The closed-loop configuration of the input buffer is facilitated by the use of an internal feedback resistor coupled from an inverting input terminal of the input buffer to the output of the input buffer, which corresponds to the inverting input terminal of the overall current feedback amplifier. The closed-loop input buffer realizes a low output impedance since the loop gain reduces the output impedance of the input buffer. With a lower output impedance, the bandwidth of the current feedback amplifier becomes more independent of the gain, even at low current implementations.

Abstract: An output stage amplifier circuit in accordance with the present invention overcomes many shortcomings of the prior art. A output stage amplifier circuit for providing a high output voltage and current reference signal suitably includes an output buffer configured with a compensation circuit for reducing disturbances introduced into the output stage amplifier circuit by voltage supply rails, such as parasitic ringing and other disturbances. The compensation circuit can suitably comprise a first compensation device, such as at least one capacitor, and a second compensation device, such as at least one capacitor. The compensation devices are suitably coupled between an input terminal of the output stage amplifier circuit and a pair of transistors proximate a pair of output transistors of the output stage amplifier circuit, and are configured to provide “pole-zero” compensation to the output stage amplifier circuit.

Abstract: A circuit for multiplexing a selected one of a plurality of input signals to an output conductor includes a plurality of diamond follower input buffers each having an input terminal coupled to receive an input signal, respectively. A diamond follower output buffer has an output coupled to the output conductor. A feedback resistor is coupled between the output conductor and the outputs of the input buffers. A first current mirror has a control input coupled to a first current bias terminal of each input buffer, and a second current error has a control input coupled to a second current bias terminal of each input buffer. The first and second current mirrors have outputs connected to drive the input of the output buffer and bias current terminals of the output buffer to provide a high slew rate.

Abstract: A bias rail buffer circuit and method in accordance with the present invention overcomes many shortcomings of the prior art. A bias rail buffer circuit for providing a reference signal is suitably configured to absorb external disturbances appearing on an output reference signal. A method for absorbing the external disturbances appearing at the output reference signal suitably includes the use of complementary transistors to source current and sink current to said output reference signal, depending on whether the external disturbances are providing a decrease or an increase to the output reference signal. The bias rail buffer circuit suitably includes an input transistor, a first pair of complementary transistors and a second pair of complementary transistors, such that the second pair of complementary transistors operate to source current and sink current to absorb external disturbances imparted on said output reference signal.

Abstract: A bias rail buffer circuit and method in accordance with the present invention overcomes many shortcomings of the prior art. A bias rail buffer circuit for providing a reference signal is suitably configured to absorb external disturbances appearing on an output reference signal. A method for absorbing the external disturbances appearing at the output reference signal suitably includes the use of complementary transistors to source current and sink current to said output reference signal, depending on whether the external disturbances are providing a decrease or an increase to the output reference signal. The bias rail buffer circuit suitably includes an input transistor, a first pair of complementary transistors and a second pair of complementary transistors, such that the second pair of complementary transistors operate to source current and sink current to absorb external disturbances imparted on said output reference signal.

Abstract: A bias rail buffer circuit and method in accordance with the present invention overcomes many shortcomings of the prior art. A bias rail buffer circuit for providing a reference signal is suitably configured to absorb external disturbances appearing on an output reference signal. A method for absorbing the external disturbances appearing at the output reference signal suitably includes the use of complementary transistors to source current and sink current to said output reference signal, depending on whether the external disturbances are providing a decrease or an increase to the output reference signal. The bias rail buffer circuit suitably includes an input transistor, a first pair of complementary transistors and a second pair of complementary transistors, such that the second pair of complementary transistors operate to source current and sink current to absorb external disturbances imparted on said output reference signal.

Abstract: A bias rail buffer circuit and method in accordance with the present invention overcomes many shortcomings of the prior art. A bias rail buffer circuit for providing a reference signal is suitably configured to absorb external disturbances appearing on an output reference signal. A method for absorbing the external disturbances appearing at the output reference signal suitably includes the use of complementary transistors to source current and sink current to said output reference signal, depending on whether the external disturbances are providing a decrease or an increase to the output reference signal. The bias rail buffer circuit suitably includes an input transistor, a first pair of complementary transistors and a second pair of complementary transistors, such that the second pair of complementary transistors operate to source current and sink current to absorb external disturbances imparted on said output reference signal.

Abstract: A current mirror circuit in accordance with the present invention overcomes many shortcomings of the prior art. A current mirror circuit for providing a current reference signal suitably includes at least one degeneration resistor to provide more degeneration for lower voltage noise while also including at least one clamping device to preventing saturation of the current mirror. The clamping device suitably comprises at least one diode, such as, for example, a Schottky-type diode. Moreover, the clamping device can be suitably configured to facilitate a higher slew rate of the current mirror circuit.

Abstract: A wideband operational amplifier in accordance with the present invention overcomes many shortcomings of the prior art. A wideband operational amplifier may be configured to provide a high output voltage and high output current. The amplifier may comprise an input stage having a first input buffer and a second input buffer, and an output stage amplifier having an output buffer. The input stage may also include current mirrors configured to facilitate a lower input offset voltage and lower input voltage noise. Moreover, the operational amplifier may also provide a wide common-mode input range and full power bandwidth simultaneously.

Abstract: A high speed integrated circuit operational amplifier chip having first, second, third and fourth successive edges includes a thermal centerline parallel to the second and fourth edges. An output driver circuit is located adjacent to an output bonding pad along the third edge and is disposed approximately symmetrically about the thermal centerline to provide approximately balanced differential heating of the operational amplifier chip relative to the thermal centerline. A low gain differential input circuit is located adjacent to the first edge and is disposed approximately symmetrically about the thermal centerline to provide approximately balanced responses of matched transistors in the low gain differential input circuit to isotherms produced by the differential heating.

Abstract: A high speed integrated circuit operational amplifier chip first, second, third and fourth successive edges includes a thermal centerline parallel to the second and fourth edges. An output driver circuit is located adjacent to an output bonding pad along the third edge and is disposed approximately symmetrically about the thermal centerline to provide approximately balanced differential heating of the operational amplifier chip relative to the thermal centerline. A differential input circuit is located adjacent to the first edge and is disposed approximately symmetrically about the thermal centerline to provide approximately balanced responses of matched transistors in the low gain differential input circuit to isotherms produced by the differential heating. The most thermally sensitive transistors are disposed along or symmetrically about the thermal centerline to provide approximately balanced response by such transistors to differential heating by the output driver circuit.

Abstract: A sampling digitizer system which may be expanded for the dynamic testing of high speed data conversion components is provided. The sampling waveform digitizer system comprises a sampling comparator for comparing a sampled input signal with a first signal. An integrator coupled to the comparator provides an output signal from the integrator and becomes the first signal. An analog to digital converter provides the digital representation of the analog waveform. A controllable delay is provided for selecting a period of time for sampling the input signal by the comparator. A control device is provided for controlling the time the comparator samples the input signal. These combination of system features allow the digitizer to receive high speed analog waveforms and convert them to an accurate digital representation of the previously described high speed analog waveform.

Abstract: In a successive approximation analogs-to-digital converter, a successive approximation register (SAR) includes an N bit, edge triggered shift register, each bit including a master-slave flip-flop. The output of each shift register bit is applied to a latch input of a D-type latch and to one input of a two-input gate that performs a logical ANDing function. Another input of the gate is connected to an output of the latch. The D input of each of the N latches is connected to an output of a corresponding comparator, which compares an analog input signal to a signal produced by an N bit digital-to-analog converter (DAC) in response to successive approximation numbers produced by the SAR. The gate outputs are connected to digital inputs of the DAC. A "0" propagates through the shift register at the DAC conversion rate.

Abstract: A 12 bit, 10 megahertz subranging analog-to-digital converter produces a sampled analog input signal. The sampled analog signal is converted by an MSB flash encoder to a 7 bit MSB word that is converted to an analog signal by a 7 bit DAC having 14 bit accuracy. The result is subtracted from the sample analog signal to produce a residue signal by means of a high speed amplifier having first and second multiplexed differential input stages, the first input stage having differential inputs receiving the sampled analog input signal and the analog signal produced by the 7 bit DAC. The second differential input stage has one input connected to ground and the other input resistively coupled to the output of the high speed amplifier. The output of the high speed amplifier is resistively coupled to the second input of the first and second differential stages. The multiplexed input high speed amplifier produces an intermediate input level until the output of the DAC is stable.

Abstract: A latching comparator has a signal input connected to the output of a device under test. A strobe input of the comparator has a strobe signal applied thereto, whereby the output of the device under test is repeatedly sampled. The output of the comparator drives an integrator, preferably through a filter. The output of the integrator drives a reference input of the comparator and a computer. The computer is driven via an A/D converter, whereby a digitized representation of the output of the device under test is provided to the computer.

Abstract: A sampling digitizer system which may be expanded for the dynamic testing of high speed data conversion components is provided. The system includes latching comparators which are supplied with the waveform under test and the comparator digital output is integrated by an operational amplifier integrator and fed back to the reference input of the latching comparator to form a comparator-integrator loop. A circuit provides strobe pulses which repeatedly sample the latch enable input of the comparators at a selected time/point until the integrator feedback forces the comparator reference input to be equal to the sample value of the input signal. At this point, an equilibrium state is reached where the integrator output oscillates about the sampled value, and when the loop settles, an analog-to-digital converter reads the final value under computer command. The sample point is computer controlled through a programmable delay line.