Patents by Inventor Joel M. Lott

Joel M. Lott has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7433192
    Abstract: An electronic module has a non-conducting substrate having at least one opening and a die/carrier assembly mounted within the opening in the substrate. The assembly has a conducting carrier and one or more integrated circuit (IC) dies mounted to the carrier. The invention may be implemented as an electronic system comprising a circuit board (CB) and at least one such electronic module mounted to the CB.
    Type: Grant
    Filed: February 10, 2005
    Date of Patent: October 7, 2008
    Assignee: Agere Systems Inc.
    Inventors: Timothy B. Bambridge, Juan A. Herbsommer, Osvaldo Lopez, Joel M. Lott, Hugo F. Safar, Thomas H. Shilling
  • Patent number: 7215204
    Abstract: An amplifier module has a substrate, as assembly having one or more integrated circuit (IC) dies mounted to the substrate, and one or more other electronic components mounted to the substrate. The assembly receives an input signal and generates an amplified output signal. The one or more other electronic components perform one or more amplifier-related functions. The amplifier module is adapted to be mounted to a circuit board (CB) as a distinct electronic package. The invention may be implemented as an electronic system having the CB and at least one such amplifier module mounted to the CB.
    Type: Grant
    Filed: February 10, 2005
    Date of Patent: May 8, 2007
    Assignee: Agere Systems Inc.
    Inventors: Timothy B. Bambridge, Juan A. Herbsommer, Osvaldo Lopez, Joel M. Lott, Khanh C. Nguyen
  • Patent number: 5422595
    Abstract: According to the present invention, a power amplifier with a plurality of power transistors has detection circuitry corresponding to each power transistor which detects the output power of the power transistors and allows this output power to be monitored and modified if desired. The detection circuitry generates a voltage output signal indicative of the rise and fall times achieved by the power transistor. The voltage output signal of the detection circuitry may be monitored by connecting the voltage output signal to a measuring device, such as an oscilloscope of built-in-test-equipment (BITE). Additionally, the voltage output signal of the detection circuitry may be modified by tuning input matching circuitry and/or output matching circuitry accordingly.
    Type: Grant
    Filed: November 24, 1993
    Date of Patent: June 6, 1995
    Assignee: SGS-Thomson Microelectronics, Inc.
    Inventor: Joel M. Lott
  • Patent number: 5315156
    Abstract: A modified transistor layout allows operation at high frequencies without adversely effecting transistor power gain. The base and collector circuits are modified in order to minimize ground bar resistance and feedback problems between the input and output circuits. This reduces the applied negative feedback and maximizes gain. The collector contact bar and the output capacitor are mounted directly on the collector island such that the output capacitor is wired directly to the grounded package metal and the collector is wired to the collector contact bar. This eliminates the need to wirebond to areas on the collector island that are covered with the eutectic run-out which results from mounting the transistor chip on the collector island.
    Type: Grant
    Filed: November 30, 1992
    Date of Patent: May 24, 1994
    Assignee: SGS-Thomson Microelectronics, Inc.
    Inventor: Joel M. Lott