Patents by Inventor Joel M. Ward

Joel M. Ward has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11950390
    Abstract: An electrical conductor assembly for use in a power distribution assembly includes an electrical conductor and a casing covering at least a portion of the electrical conductor. A spring member is mounted to the casing and configured to apply a compressive force to the electrical conductor.
    Type: Grant
    Filed: October 28, 2020
    Date of Patent: April 2, 2024
    Assignee: EATON INTELLIGENT POWER LIMITED
    Inventors: Joel Anthony Furco, Andrew Francis Scarlata, Joseph M. Manahan, Patrick S. Ward
  • Publication number: 20240097384
    Abstract: An electrical conductor assembly for use in a power distribution assembly includes an electrical conductor. A casing covers at least a portion of the electrical conductor. The casing insulates the at least a portion of the electrical conductor.
    Type: Application
    Filed: November 29, 2023
    Publication date: March 21, 2024
    Inventors: Joel Anthony Furco, Joseph M. Manahan, Patrick S. Ward
  • Patent number: 5894560
    Abstract: An apparatus and method for improving the input/output performance of a computer system under the control of a multi-tasking, multi-threaded operating system. In particular, the invention provides an apparatus and method to chain contiguous DMA scatter gather sub blocks of a PRD table for channel 0 with contiguous DMA scatter gather sub blocks of a PRD table for channel 1, using a single data manager, while maintaining maximum media bandwidth. DMA block transfers are scheduled based on the availability of data from the I/O device's buffer memory, thus minimizing both media or network idle time as well as minimizing I/O bus idle time. Near maximum aggregate bandwidth of multiple I/O buses and their associated devices is obtained. The apparatus and method thus provides significant performance advantages over prior techniques having two I/O channel systems implemented with a single data manager.
    Type: Grant
    Filed: August 26, 1996
    Date of Patent: April 13, 1999
    Assignee: LSI Logic Corporation
    Inventors: Richard D. Carmichael, Joel M. Ward, Michael A. Winchell
  • Patent number: 5864712
    Abstract: A method an corresponding apparatus for improving the input/output performance of a computer system under the control of a multi-tasking, multi-threaded operating system. In particular, the invention provides an apparatus and method to interleave contiguous DMA scatter/gather sub blocks of a PRD table corresponding to a first I/O channel with contiguous DMA scatter/gather sub blocks of a PRD table corresponding to a second I/O channel, using a single data manager, while maintaining maximum media bandwidth. DMA block transfers are scheduled by the single data manager based on the availability of data from the I/O devices' buffer memories, thus minimizing both media or network idle time as well as minimizing I/O bus idle time. Near maximum aggregate bandwidth of multiple I/O buses and their associated devices is obtained. The apparatus and method thus provides significant performance advantages over prior techniques having two I/O channel systems implemented with a single data manager.
    Type: Grant
    Filed: December 31, 1996
    Date of Patent: January 26, 1999
    Assignee: LSI Logic Corporation
    Inventors: Richard D. Carmichael, Joel M. Ward, Michael A. Winchell