Abstract: An amplifier includes first through sixth transistors. The first transistor is of a first polarity type and has a control terminal and first and second terminals. The second transistor is of a second polarity type and has a control terminal and first and second terminals. The third transistor is of the first polarity type and has a control terminal and first and second terminals. The second terminal of the third transistor is coupled to the first terminal of the second transistor. The fourth transistor is of the second polarity type and has a control terminal and first and second terminals. The first terminal of the fourth transistor is coupled to the second terminal of the second transistor. The fifth transistor has a control terminal coupled to the control terminal of the third transistor. A sixth transistor has a control terminal coupled to the control terminal of the fourth transistor.

Abstract: A fully-differential amplifier (FDA) includes a core differential amplifier and a common-mode input voltage control circuit. The core differential amplifier includes differential inputs. The common-mode input voltage control circuit is coupled to the differential inputs. The common-mode input voltage control circuit is configured to generate an error signal as a difference of an input common mode voltage at the differential inputs and a target common mode input voltage (VICM); and to adjust the input common mode voltage to the VICM based on the error signal.

Abstract: Examples of amplifiers accurately generate control currents for control terminals of output drivers using current-replication transistors and current mirrors. An input terminal of a first current mirror is coupled to the control terminal of a first current-replication transistor, and an input terminal of a second current mirror is coupled to the control terminal of a second current-replication transistor. The output terminals of the first and second current mirrors are coupled to the control terminals of first and second output drivers, respectively. First and second intermediate currents indicative of first and second currents flowing to the first and second output driver elements, respectively, are generated. Using the first and second current mirrors, first and second control currents are generated to control the first and second output driver elements, respectively, by scaling the first and second intermediate currents according to the gain factors of the current mirrors.

Abstract: Examples of amplifiers use current-replication transistors and a separation circuit coupled to such transistors to separate error current components from other current components in a pre-driver of an amplifier. In response to driving the current-replication transistors with the separated error current components, replica base current components that approximate error-modulation components of the pre-driver base currents are generated. Replica-current subtraction circuitry coupled to the current-replication transistors then subtract the replica base current components from the pre-driver base currents, affecting cancellation of the error-modulation components of the pre-driver base currents.

Abstract: In one example an electronic device includes a first resistor and a second resistor. The first resistor includes a first resistive layer located over a substrate, the first resistive layer having a first sheet resistance. The second resistor includes a first portion of a second resistive layer located over the substrate, the second resistive layer having a second sheet resistance different from the first sheet resistance. The first resistive layer is located between the substrate and a second noncontiguous portion of the second resistive layer.

Abstract: Examples of amplifiers use current-replication transistors and a separation circuit coupled to such transistors to separate error current components from other current components in a pre-driver of an amplifier. In response to driving the current-replication transistors with the separated error current components, replica base current components that approximate error-modulation components of the pre-driver base currents are generated. Replica-current subtraction circuitry coupled to the current-replication transistors then subtract the replica base current components from the pre-driver base currents, affecting cancellation of the error-modulation components of the pre-driver base currents.

Abstract: Examples of amplifiers accurately generate control currents for control terminals of output drivers using current-replication transistors and current mirrors. An input terminal of a first current mirror is coupled to the control terminal of a first current-replication transistor, and an input terminal of a second current mirror is coupled to the control terminal of a second current-replication transistor. The output terminals of the first and second current mirrors are coupled to the control terminals of first and second output drivers, respectively. First and second intermediate currents indicative of first and second currents flowing to the first and second output driver elements, respectively, are generated. Using the first and second current mirrors, first and second control currents are generated to control the first and second output driver elements, respectively, by scaling the first and second intermediate currents according to the gain factors of the current mirrors.

Abstract: A fully-differential amplifier (FDA) includes a core differential amplifier and a common-mode input voltage control circuit. The core differential amplifier includes differential inputs. The common-mode input voltage control circuit is coupled to the differential inputs. The common-mode input voltage control circuit is configured to generate an error signal as a difference of an input common mode voltage at the differential inputs and a target common mode input voltage (VICM); and to adjust the input common mode voltage to the VICM based on the error signal.

Abstract: In one example an electronic device includes a first resistor and a second resistor. The first resistor includes a first resistive layer located over a substrate, the first resistive layer having a first sheet resistance. The second resistor includes a first portion of a second resistive layer located over the substrate, the second resistive layer having a second sheet resistance different from the first sheet resistance. The first resistive layer is located between the substrate and a second noncontiguous portion of the second resistive layer.

Abstract: A method of forming an electronic device includes forming an opening through a dielectric layer located over a first resistive layer, the first resistive layer having a first sheet resistance. A second resistive layer is deposited over the dielectric layer and into the opening. The second resistive layer has a second sheet resistance different from the first sheet resistance. A portion of the second resistive layer is removed, thereby forming first and second noncontiguous portions of the second resistive layer, wherein the second portion of the second resistive layer contacts the first resistive layer.

Abstract: A method of forming an electronic device includes forming first, second and third doped regions at a surface of a semiconductor substrate. A first buried layer is located within the semiconductor substrate below the first, second and third doped regions. Fourth and fifth doped regions are laterally spaced apart along the substrate and extend from the surface of the substrate to the first buried layer, the first, second and third doped regions being located between the fourth and fifth doped regions. A second buried layer is formed within the substrate and between the fourth and fifth doped regions such that a first portion of the semiconductor substrate is located between the first buried layer and the second buried layer, and a second portion of the semiconductor substrate is located between the first, second and third doped regions and the second buried layer.

Abstract: A method of forming an electronic device includes forming first, second and third doped regions at a surface of a semiconductor substrate. A first buried layer is located within the semiconductor substrate below the first, second and third doped regions. Fourth and fifth doped regions are laterally spaced apart along the substrate and extend from the surface of the substrate to the first buried layer, the first, second and third doped regions being located between the fourth and fifth doped regions. A second buried layer is formed within the substrate and between the fourth and fifth doped regions such that a first portion of the semiconductor substrate is located between the first buried layer and the second buried layer, and a second portion of the semiconductor substrate is located between the first, second and third doped regions and the second buried layer.

Abstract: A semiconductor device contains a JFET with a channel layer having a first conductivity type in a substrate. The JFET has a back gate having a second, opposite, conductivity type below the channel. The back gate is laterally aligned with the channel layer. The semiconductor device is formed by forming a channel mask over the substrate of the semiconductor device which exposes an area for the channel dopants. The channel dopants are implanted into the substrate in the area exposed by the channel mask while the channel mask is in place. The back gate dopants are implanted into the substrate while the channel mask is in place, so that the implanted channel dopants are laterally aligned with the implanted channel dopants.

Abstract: An electronic device includes a first resistor and a second resistor. The first resistor includes a first resistive layer located over a substrate and having a first sheet resistance. The second resistor includes a first portion of a second resistive layer located over the substrate and having a second sheet resistance that is different from the first sheet resistance. The first resistive layer is located between the substrate and a second noncontiguous portion of the second resistive layer.

Abstract: An integrated circuit includes a higher sheet resistance resistor and a lower sheet resistance resistor, disposed in a same level of dielectric layers of the integrated circuit. The higher sheet resistor has a body region and head regions in a higher sheet resistance layer. The lower sheet resistor has a body region and head regions in a lower sheet resistance layer, which is thicker than the higher sheet layer. The higher sheet resistor has an upper head layer contacting the higher sheet layer at each head region of the higher sheet layer. Each upper head layer has a same composition and thickness as the lower sheet layer of the lower sheet resistor. The lower sheet resistor is free of head layers over the lower sheet resistance layer.

Abstract: An integrated circuit includes a higher sheet resistance resistor and a lower sheet resistance resistor, disposed in a same level of dielectric layers of the integrated circuit. The higher sheet resistor has a body region and head regions in a higher sheet resistance layer. The lower sheet resistor has a body region and head regions in a lower sheet resistance layer, which is thicker than the higher sheet layer. The higher sheet resistor has an upper head layer contacting the higher sheet layer at each head region of the higher sheet layer. Each upper head layer has a same composition and thickness as the lower sheet layer of the lower sheet resistor. The lower sheet resistor is free of head layers over the lower sheet resistance layer.

Abstract: A semiconductor device contains a JFET with a channel layer having a first conductivity type in a substrate. The JFET has a back gate having a second, opposite, conductivity type below the channel. The back gate is laterally aligned with the channel layer. The semiconductor device is formed by forming a channel mask over the substrate of the semiconductor device which exposes an area for the channel dopants. The channel dopants are implanted into the substrate in the area exposed by the channel mask while the channel mask is in place. The back gate dopants are implanted into the substrate while the channel mask is in place, so that the implanted channel dopants are laterally aligned with the implanted channel dopants.

Abstract: A bus driver circuit (FIG. 2) is disclosed. The circuit includes a signal lead of a bus (200) and a reference terminal (Vss). A first transistor (MN0) has a first control terminal and has a first current path coupled to the reference terminal. A second transistor (MN1) has a second control terminal coupled to the first control terminal and has a second current path coupled between the signal lead and the reference terminal. A third transistor (MP0) is arranged to provide a first current through the first current path when the signal lead is in a first logic state (high). A fourth transistor (MP1) is arranged to apply a voltage to the second control terminal when the signal lead is in a second logic state (low).

Abstract: A bus driver circuit (FIG. 2) is disclosed. The circuit includes a signal lead of a bus (200) and a reference terminal (Vss). A first transistor (MN0) has a first control terminal and has a first current path coupled to the reference terminal. A second transistor (MN1) has a second control terminal coupled to the first control terminal and has a second current path coupled between the signal lead and the reference terminal. A third transistor (MP0) is arranged to provide a first current through the first current path when the signal lead is in a first logic state (high). A fourth transistor (MP1) is arranged to apply a voltage to the second control terminal when the signal lead is in a second logic state (low).

Abstract: A system and method for implementing an amplifier capable of limiting or clamping an amplifier output signal is described. A clamp buffer and an input buffer cooperate to bias an output circuit according to the relative level of a clamp signal and an input signal. In a normal mode, in which the input signal has a first relationship with the clamp signal, the output circuit provides an output signal based on the input signal. In a clamping mode, in which the input signal has a second relationship with the clamp signal, the output circuit provides an output signal based on the clamp signal, which can be substantially fixed. The clamp signal can be set by the user to establish a desired clamping range.