Abstract: An element to be used as an anode in a lithium-ion battery comprising a lithiated single crystal porous-silicon layer made on the surface of a p-doped single crystal Si of thickness 25-1000 mm and resistivity of less than 0.01-ohm cm. Successful lithiation is achieved either electrochemically or by direct alloying of lithium metal with the porous-Si with a wide range of porosities. The lithiated silicon anode allows a high cathode loading in a lithium-ion battery resulting in record current densities without the formation of lithium dendrites.

Abstract: An element to be used as an anode in a lithium-ion battery comprising an electrochemically lithiated thick or thin p or n-doped virgin single crystal Si with or without an oxide on the upper surface thereof. The lithiated structure further has a plurality of single crystalline p or n-doped Si particles dispersed over a non-lithium reactive reacting electrically conductive adhesive positioned atop a current collector.

Abstract: A Phase-Change Memory (PCM) device includes a dielectric layer, a bottom electrode disposed in the dielectric layer, a liner material disposed on the bottom electrode, a phase-change material disposed on the liner material, and a top electrode disposed on the phase-change material and in the dielectric layer.

Abstract: Embodiments of the invention provide a resistive switching device that includes a metal interconnect electrode and a memory stack over the metal interconnect electrode. The memory stack includes a plurality of layers that includes a top electrode, a plasma-treated bottom electrode, and a dielectric layer between the top electrode and the plasma-treated bottom electrode. The plasma-treated bottom electrode includes a portion of a blanket bottom electrode layer. The plasma-treated bottom electrode further includes a current-conducting filament characteristic that results from a charge particle treatment applied to the blanket bottom electrode while a top surface of the blanket bottom electrode is exposed.

Abstract: A silicon-based electrode forms an interface with a layer pair being: 1. a thin, semi-dielectric layer made of a lithium (Li) compound, e.g. lithium fluoride, LiF, disposed on and adheres to the electrode surface of the silicon-based electrode and 2. an molten-ion conductive layer of a lithium containing salt (lithium salt layer) disposed on the semi-dielectric layer. One or more device layers can be disposed on the layer pair to make devices such as energy storage devices, like batteries. The interface has a low resistivity that reduces the energy losses and generated heat of the devices.

Abstract: Provided are embodiments for a semiconductor device. The semiconductor device includes a bottom electrode, wherein the bottom electrode is formed on a metal interconnect electrode, and a dielectric layer on a surface of the bottom electrode. The semiconductor device also includes a top electrode formed on a surface of the dielectric layer, wherein at least one of the top electrode or the bottom electrode is a plasma treated top electrode or plasma treated bottom electrode. Also provided are embodiments for a method of fabricating a resistive switching device where at least one of the plurality of layers of the memory stack is processed with a charge particle treatment.

Abstract: Methods of forming a controllable resistive element include forming source and drain regions in a substrate. A battery stack is formed on a substrate between the source and drain regions. Respective anode and cathode electrical connections are formed to the battery stack. Respective source and drain electrical connections are formed.

Abstract: A semiconductor device includes an extremely thin semiconductor-on-insulator substrate (ETSOI) having a base substrate, a thin semiconductor layer and a buried dielectric therebetween. A device channel is formed in the thin semiconductor layer. Source and drain regions are formed at opposing positions relative to the device channel. The source and drain regions include an n-type material deposited on the buried dielectric within a thickness of the thin semiconductor layer. A gate structure is formed over the device channel.

Abstract: A semiconductor device includes a field-effect transistor, a first back-end-of-line (BEOL) metallization level and a second BEOL metallization level disposed above the first BEOL metallization level. A portion of the field-effect transistor includes lithium therein, and the field-effect transistor is integrated between the first and second BEOL metallization levels. The portion of the field-effect transistor including the lithium therein can be a channel layer, or a source and/or drain region.

Abstract: An energy storage device is provided that includes a pre-lithiated silicon based anode and a carbon nanotube based cathode. The pre-lithiated silicon anode has a porous region and a non-porous region. The full cell energy storage device has high electrochemical performance which exhibits greater 200 rechargeable cycles with less than 25% after 10 charge discharge cycles relative to the first discharge cycle, a maximum specific discharge capacity greater than 300 mAh/g and a specific capacity of greater than 100 mAh/g for over 130 cycles. Such an energy storage device is scalable for a wide array of applications due to its wafer level processing and silicon-based substrate integrability.

Abstract: A battery includes a cathode with a metal halide and an electrically conductive material, wherein the metal halide acts as an active cathode material; a porous silicon anode with a surface having pores with a depth of about 0.5 microns to about 500 microns, and a metal on the surface and in at least some of the pores thereof; and an electrolyte contacting the anode and the cathode, wherein the electrolyte includes a nitrile moiety.

Abstract: A catholyte-like material including a cathode material and an interfacial additive layer for providing a lithium ion energy storage device having low impedance is disclosed. The interfacial additive layer, which is composed of vapor deposited iodine, is present between the cathode material and an electrolyte layer of the device. The presence of such an interfacial additive layer increases the ion and electron mobile dependent performances at the cathode material interface due to significant decrease in the resistance/impedance that is observed at the respective interface as well as the impedance observed in the bulk of the device. The catholyte-like material of the present application can be used to provide a lithium ion energy storage device having high charge/discharge rates and/or high capacity.

Abstract: An interfacial additive layer for decreasing the interfacial resistance/impedance of a silicon based electrode-containing device such as, for example, an energy storage device or a micro-resistor, is disclosed. The interfacial additive layer, which is composed of a molten lithium containing salt, is formed between a silicon based electrode and a solid polymer electrolyte layer of the device. The presence of such an interfacial additive layer increases the ion and electron mobile dependent performances at the silicon based electrode interface due to significant decrease in the resistance/impedance that is observed at the respective interface as well as the impedance observed in the bulk of the device.

Abstract: A Phase-Change Memory (PCM) device includes a dielectric layer, a bottom electrode disposed in the dielectric layer, a liner material disposed on the bottom electrode, a phase-change material disposed on the liner material, and a top electrode disposed on the phase-change material and in the dielectric layer.

Abstract: A silicon-based electrode forms an interface with a layer pair being: 1. a thin, semi-dielectric layer made of a lithium (Li) compound, e.g. lithium fluoride, LiF, disposed on and adheres to the electrode surface of the silicon-based electrode and 2. an molten-ion conductive layer of a lithium containing salt (lithium salt layer) disposed on the semi-dielectric layer. One or more device layers can be disposed on the layer pair to make devices such as energy storage devices, like batteries. The interface has a low resistivity that reduces the energy losses and generated heat of the devices.

Abstract: A method of forming a semiconductor structure includes forming at least one trench in a non-porous silicon substrate, the at least one trench providing an energy storage device containment feature. The method also includes forming an electrical and ionic insulating layer disposed over a top surface of the non-porous silicon substrate. The method further includes forming, in at least a base of the at least one trench, a porous silicon layer of unitary construction with the non-porous silicon substrate. The porous silicon layer provides at least a portion of a first active electrode for an energy storage device disposed in the energy storage device containment feature.

Abstract: A device such as, for example, an energy storage device or a micro-resistor, is disclosed which includes a silicon based electrode in which decreased interfacial resistance/impedance throughout the charge-mobile region of the device is provided. The decreased interfacial resistance/impedance is provided by forming an interfacial additive composite layer composed of a molten lithium containing salt layer and a layer of a Li-salt containing conductive polymeric adhesive material between the silicon based electrode and a solid polymer electrolyte layer. The presence of such an interfacial additive composite layer increases the ion and electron mobile dependent performances at the silicon based electrode interface due to significant decrease in the resistance/impedance that is observed at the respective interface as well as the impedance observed in the bulk of the device.

Abstract: Provided are embodiments for a semiconductor device. The semiconductor device includes a bottom electrode, wherein the bottom electrode is formed on a metal interconnect electrode, and a dielectric layer on a surface of the bottom electrode. The semiconductor device also includes a top electrode formed on a surface of the dielectric layer, wherein at least one of the top electrode or the bottom electrode is a plasma treated top electrode or plasma treated bottom electrode. Also provided are embodiments for a method of fabricating a resistive switching device where at least one of the plurality of layers of the memory stack is processed with a charge particle treatment.

Abstract: A semiconductor device includes a monocrystalline substrate configured to form a channel region between two recesses in the substrate. A gate conductor is formed on a passivation layer over the channel region. Dielectric pads are formed in a bottom of the recesses and configured to prevent leakage to the substrate. Source and drain regions are formed in the recesses on the dielectric pads from a deposited non-crystalline n-type material with the source and drain regions making contact with the channel region.

Abstract: Embodiments of the invention are directed to a resistive switching device (RSD). A non-limiting example of the RSD includes a fin-shaped element formed on a substrate, wherein the fin-shaped element includes a source region, a central channel region, and a drain region. A gate is formed over a top surface and sidewalls of the central channel region. The fin-shaped element is doped with impurities that generate interstitial charged particles configured to move interstitially through a lattice structure of the fin-shaped element under the influence of an electric field applied to the RSD.