Abstract: A network arrangement uses a poll select control protocol and a loop back arrangement at each node for equalizing transmission delay from each node to a central station. Delays at each node can be adjusted to start timing in response to a broadcast signal indicating an amount of delay to be applied from the start of a synchronization interval to the beginning of transmission of data collected at the nodes. The arrangement is particularly useful in the field of data acquisition and particularly in the area of seismic sensing.

Abstract: A power on reset circuit, preferably for an integrated circuit, detects application of voltage, starts a phase locked loop one application of voltage is detected but inhibits all clock used for digital logic operations until voltage stability is achieved. If a switched converter is used, the duty cycle of the switched converter is held at unity for a period of time before it is set to that needed to achieve the desired chip operating voltage. Clocks controlling other circuits can be released in stages after the duty cycle of the switched converter is set to its operating voltage level.

Abstract: A low power programmable digital filter integrated circuit architecture has a programmable front end servicing up to 4 digital sources. Changing the programming of the front end permits digital outputs from different sensor types to be accommodated. Digital filtering is accomplished using a digital signal processor that is programmable to accommodate different decimation ratios. A serial data output register receives the filtered digital signals and provides them to an output port. The digital filter integrated circuit may be connected in a token passing configuration with other digital filter integrated circuits to increase the number of sources accommodated.

Abstract: A low power programmable digital filter integrated circuit architecture has a programmable front end servicing up to 4 digital sources. Changing the programming of the front end permits digital outputs from different sensor types to be accommodated. Digital filtering is accomplished using a digital signal processor that is programmable to accommodate different decimation ratios.

Abstract: A network arrangement uses a poll select control protocol and a loop back arrangement at each node for equalizing transmission delay from each node to a central station. Delays at each node can be adjusted to start timing in response to a broadcast signal indicating an amount of delay to be applied from the start of a synchronization interval to the beginning of transmission of data collected at the nodes. The arrangement is particularly useful in the field of data acquisition and particularly in the area of seismic sensing.

Abstract: A network arrangement uses a poll select control protocol and a loop back arrangement at each node for equalizing transmission delay from each node to a central station. Delays at each node can be adjusted to start timing in response to a broadcast signal indicating an amount of delay to be applied from the start of a synchronization interval to the beginning of transmission of data collected at the nodes. The arrangement is particularly useful in the field of data acquisition and particularly in the area of seismic sensing.

Abstract: A sinc filter is implemented by partitioning 1 bit wide incoming data into multibit words. The multibit words are multiplied by respective coefficient sets. Some multibit words are twisted by inverting the bit order and the multiplied using the same coefficient sets used for untwisted words. Multiplications are implemented using either look up tables or logic and the filter is implemented using only shifts and additions. The sinc filter is particularly useful applications in the field of data acquisition and particularly in the area of seismic sensing.

Abstract: A low power programmable digital filter integrated circuit architecture has a programmable front end servicing up to 4 digital sources. Changing the programming of the front end permits digital outputs from different sensor types to be accommodated. Digital filtering is accomplished using a digital signal processor that is programmable to accommodate different decimation ratios. A serial data output register receives the filtered digital signals and provides them to an output port. The digital filter integrated circuit may be connected in a token passing configuration with other digital filter integrated circuits to increase the number of sources accommodated.

Abstract: Clocks on and off an integrated circuit chip are aligned to that clocks on the chip are synchronized to one of the rising and falling edges of a master clock and those off the chip are synchronized to the other of the rising and falling edges of the master clock. This permits a certain ease of interfacing circuits controlled by those clocks. Programmable clocks on the chip can be reprogrammed during operation to conserve power.

Abstract: A sinc filter is implemented by partitioning 1 bit wide incoming data into multibit words. The multibit words are multiplied by respective coefficient sets. Some multibit words are twisted by inverting the bit order and the multiplied using the same coefficient sets used for untwisted words. Multiplications are implemented using either look up tables or logic and the filter is implemented using only shifts and additions. The sinc filter is particularly useful applications in the field of data acquisition and particularly in the area of seismic sensing.

Abstract: A data acquisition system has a central station connected to a plurality of nodes over a network. Each node is connected to receive signals from one or more sensors ad each is configured to have substantially the same transmission delay to said central station. The central station is configured to notify all nodes of an event time at which a data event, such as a seismic shot, occurred.

Abstract: A phase shifter is implemented using a polyphase filter. The filter is preferably a linear phase Finite Impulse Response (FIR) filter. The amount of delay imparted by the phase shifter is determined by a particular set of coefficients selected from a plurality of such coefficients. Storage requirements are reduced by taking advantage of symmetries in the coefficients for the filters. Memory requirements are further reduced by partitioning the polyphase filter into two polyphase filters and using one to set a rough delay amount and the other to set a fine delay amount between rough delay amount settings. The particular amount of delay may be set by an external synchronization signal.

Abstract: A decimation filter implements selective decimation ratios by arranging a plurality of sinc filters in different pipeline arrangements to produce the desired ratio. Power savings area achieved by implementing the sinc filters as FIR sinc filters and by implementing multiplications using look up tables. One approach uses a fixed first stage filter and one or more second stage sinc filters selected from the group comprising two 4th order, 5 tap sinc filters, a 4th order, 9 tap sinc filter; a 5th order, 6 tap sinc filter and a 6th order 7 tap sinc filter. The sinc filter is particularly useful applications in the field of data acquisition and particularly in the area of seismic sensing.

Abstract: A switched converter uses two series connected complementary CMOS devices and has a square wave source for activating one CMOS device while deactivating the other; and a break before make circuit connected between the square wave source and said complementary CMOS devices to ensure that one device is substantially completely off before the other device turns on. The switched converter is programmable as to frequency, phase and duty cycle.

Abstract: A multiply add carry (MAC) circuit correctly determines the value of a carry bit when an operation X*Y+Z is undertaken, where X, Y and Z are real numbers and where an accumulator and rounding are utilized. The circuit (1) determines if the product X*Y is negative, (2) determines if the value in the accumulator is negative, (3) determines if a round bit propagates all the way to the most significant bit (MSB) position, (4) determines if the result X*Y+Accumulator+round is negative; and (5) determines a correct carry bit based on the other determinations.