Patents by Inventor Joel Paul Jenkins

Joel Paul Jenkins has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Switched phase and frequency detector based DPLL circuit with excellent wander and jitter performance and fast frequency acquisition
    Patent number: 8111106
    Abstract: Some embodiments of the present invention may include a DPLL circuit comprising a firmware. The firmware may comprise a re-sampled NCO phase detector capable of receiving a reference clock timing signal and a VCXO clock timing signal. The re-sampled NCO phase detector may comprise a resampler capable of receiving phase output and the VCXO clock timing signal and resampling the phase output; and a subtractor capable of receiving the resampled phase output and subtracting the resampled phase output from a calculated mean value of the phase output. The firmware may further comprise a frequency detector capable of receiving the reference clock timing signal and the VCXO clock timing signal; and a multiplexer capable of switching between the re-sampled NCO phase detector and the frequency detector dependent upon a frequency lock status.
    Type: Grant
    Filed: March 2, 2010
    Date of Patent: February 7, 2012
    Assignee: Cisco Technology, Inc.
    Inventors: Leo Montreuil, Larry Stephen McKinney, Jiening Ao, Joel Paul Jenkins
  • NOVEL SWITCHED PHASE AND FREQUENCY DETECTOR BASED DPLL CIRCUIT WITH EXCELLENT WANDER AND JITTER PERFORMANCE AND FAST FREQUENCY ACQUISITION
    Publication number: 20110215873
    Abstract: Some embodiments of the present invention may include a DPLL circuit comprising a firmware. The firmware may comprise a re-sampled NCO phase detector capable of receiving a reference clock timing signal and a VCXO clock timing signal. The re-sampled NCO phase detector may comprise a resampler capable of receiving phase output and the VCXO clock timing signal and resampling the phase output; and a subtractor capable of receiving the resampled phase output and subtracting the resampled phase output from a calculated mean value of the phase output. The firmware may further comprise a frequency detector capable of receiving the reference clock timing signal and the VCXO clock timing signal; and a multiplexer capable of switching between the re-sampled NCO phase detector and the frequency detector dependent upon a frequency lock status.
    Type: Application
    Filed: March 2, 2010
    Publication date: September 8, 2011
    Applicant: Cisco Technology, Inc.
    Inventors: Leo Montreuil, Larry Stephen McKinney, Jiening Ao, Joel Paul Jenkins