Patents by Inventor JOEL R. KNIGHT

JOEL R. KNIGHT has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Secure low voltage testing
    Patent number: 9891277
    Abstract: An integrated circuit includes a normal voltage detector configured to detect a normal voltage at which the integrated circuit being fully functional. A first voltage detector detects a first voltage that is less than the normal voltage. A second voltage detector detects a second voltage that is less than the first voltage. A reset module is coupled to a supply voltage, the normal voltage detector, the first voltage detector, and the second voltage detector. The reset module includes test logic to, when the supply voltage rises to the first voltage from the second voltage, perform a pass/fail test when the integrated circuit is in a pass/fail test mode, and perform a power up reset when the integrated circuit in not in the pass/fail test mode.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: February 13, 2018
    Assignee: NXP USA, Inc.
    Inventors: Joel R. Knight, James B. Eifert, Stefano Pietri, Steven K. Watkins
  • SECURE LOW VOLTAGE TESTING
    Publication number: 20160091561
    Abstract: An integrated circuit includes a normal voltage detector configured to detect a normal voltage at which the integrated circuit being fully functional. A first voltage detector detects a first voltage that is less than the normal voltage. A second voltage detector detects a second voltage that is less than the first voltage. A reset module is coupled to a supply voltage, the normal voltage detector, the first voltage detector, and the second voltage detector. The reset module includes test logic to, when the supply voltage rises to the first voltage from the second voltage, perform a pass/fail test when the integrated circuit is in a pass/fail test mode, and perform a power up reset when the integrated circuit in not in the pass/fail test mode.
    Type: Application
    Filed: September 30, 2014
    Publication date: March 31, 2016
    Inventors: JOEL R. KNIGHT, JAMES B. EIFERT, STEFANO PIETRI, STEVEN K. WATKINS