Abstract: A data processor system having a total memory capacity, an integrated circuit chip having thereon a central processing unit (CPU), a ROM, a RAM, a first decoder responsive to addresses supplied thereto for determining the location of the RAM in the total memory capacity, and logic for disabling the ROM from the CPU and for relocating the RAM in the total memory capacity. Also provided are a generator for generating a first control signal having first and second states, first gating logic responsive to the first state of the control signal to disable the ROM and to disconnect the output of the first decoder from the RAM.

Abstract: In a data processing system having a memory and employing N-bit bytes and two byte addresses, a branch instruction which can cross one page boundary is executed without having to use calculations to effect a change in the contents of the program counter (PC). It is determined whether the value V1 of the (N-1) least significant bits (LSB's ) of the lower order byte of the two byte branch address is greater or less than the value V2 of the (N-1) least significant bits (LSB's) of the lower order byte of the address to which the PC is pointing and also whether PC N.noteq.BR N where PC N and BR N are the most significant bits of the lower order bytes of the PC address and the branch address, respectively. If V1<V2, PC N=1, and PC N.noteq.BR N, the upper order byte of the PC address is incremented by 1 and if V1>V2, PC N=0, and PC N.noteq.BR 7, the upper order byte of the PC address is decremented by 1.