Patents by Inventor Joel Reuben Phillips

Joel Reuben Phillips has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12141233
    Abstract: Disclosed are methods, systems, and articles of manufacture for characterizing an electronic design with an MOR-based envelope Fourier technique. Multiple training models may be determined at multiple time points for an electronic circuit by using at least the MOR-based envelope Fourier technique that comprises a harmonic balance technique. A training model of the multiple training models may be reduced into a reduced order training model in a reduced order space at least by applying at least model order reduction of the MOR-based envelope Fourier technique to the training model. A time varying system may be determined for the electronic circuit based by using at least the reduced order training model.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: November 12, 2024
    Assignee: Cadence Design Systems, Inc.
    Inventors: Marco Tony Lloyd Kassis, Mina Adel Aziz Farhan, Joel Reuben Phillips
  • Patent number: 10423744
    Abstract: A system, method, and computer program product for reduced resource harmonic balance circuit simulations is disclosed, wherein a lattice structure is implemented in place of conventional approaches in order to reduce the amount of data being processed in each iteration of the harmonic balance process. Additionally, sparse frequency cuts, which correspond to the lattice structures, are disclosed. The sparse frequency cuts and the lattice structure may be may be customized, modified, and/or adjusted to match a variety of circuits with non-linear components, such as those found in microwave, RF, and multicarrier (e.g. LTE) implementations.
    Type: Grant
    Filed: January 28, 2015
    Date of Patent: September 24, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Joel Reuben Phillips, Jun Meng, Yunbo Pang
  • Patent number: 8180621
    Abstract: A method of simulating parametric variations in an integrated circuit (IC) includes: specifying an IC model, wherein the IC model includes one or more parameters for variation about a nominal condition; calculating parametric perturbations about the nominal condition; and saving one or more values for the parametric perturbations in a computer-readable medium. Calculating the parametric perturbations includes: simulating the nominal condition for the IC; determining perturbation values for the IC model about the nominal conditions, wherein the perturbation values include linear time-varying matrices and parametric right-hand sides, determining a performance metric for the IC and a performance sampling vector for sampling the performance metric about the nominal condition from the perturbation values; and determining voltage-sensitivity values and performance-sensitivity values from the perturbation values and the performance-sampling vector.
    Type: Grant
    Filed: September 12, 2008
    Date of Patent: May 15, 2012
    Assignee: Cadence Design Systems, Inc.
    Inventor: Joel Reuben Phillips
  • Publication number: 20090228250
    Abstract: A method of simulating parametric variations in an integrated circuit (IC) includes: specifying an IC model, wherein the IC model includes one or more parameters for variation about a nominal condition; calculating parametric perturbations about the nominal condition; and saving one or more values for the parametric perturbations in a computer-readable medium. Calculating the parametric perturbations includes: simulating the nominal condition for the IC; determining perturbation values for the IC model about the nominal conditions, wherein the perturbation values include linear time-varying matrices and parametric right-hand sides, determining a performance metric for the IC and a performance sampling vector for sampling the performance metric about the nominal condition from the perturbation values; and determining voltage-sensitivity values and performance-sensitivity values from the perturbation values and the performance-sampling vector.
    Type: Application
    Filed: September 12, 2008
    Publication date: September 10, 2009
    Applicant: CADENCE DESIGN SYSTEMS, INC.
    Inventor: Joel Reuben Phillips