Abstract: The operating potential to a storage element is supplied via an impedance element connected between a source of operating potential and a first power terminal of the storage element adapted to receive an operating potential. Information is written into the storage element via a gating transistor having its conduction path connected between an input line and a data input point to the storage element. Write circuitry includes means connected between the first power terminal and the input line. During a write operation, the write circuit, while applying the desired bit of information to the cell input, causes current to flow through the impedance element lowering the potential across the flip-flop until the desired bit of information is written into the cell.

Abstract: A memory array includes row conductors which have to be charged to a first level prior to each read-out cycle. During a read-out cycle the row conductors may or may not be discharged to a second level depending on whether a "1" or a "0" is stored at selected bit locations. The memory array also includes "dummy" row conductors which are discharged to the second level each time the contents of the array are read out. Means are provided for charging the row conductors including the "dummy" row conductors to the first level prior to each read-out, for sensing the charge level on the "dummy" row conductors, and for terminating the charging cycle when the charge level on the "dummy" row conductors reaches the first level.