Patents by Inventor Joel T. Yuen

Joel T. Yuen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for scan design using a formal verification-based process
    Patent number: 6748352
    Abstract: A scan cell design approach includes removing a formal verification property associated with a scan cell from a set of formal verification properties to create a reduced set of formal verification properties. A formal verification assumption verification process is then performed on a schematic using assumptions generated from the reduced set of formal verification properties. An output of the assumption verification process indicates whether there is a potential contention site at logic coupled to the output of the scan cell.
    Type: Grant
    Filed: December 30, 1999
    Date of Patent: June 8, 2004
    Assignee: Intel Corporation
    Inventors: Joel T. Yuen, Kailasnath S. Maneparambil, Puneet Singh