Patents by Inventor Joemar Sinipete
Joemar Sinipete has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240087663Abstract: Methods, systems, and devices related to built-in self-test (BIST) circuitry of a controller. The controller can be coupled to multiple memory devices. The BIST circuitry can include registers configured to store burst patterns. The BIST circuitry can perform a BIST operation on the memory devices contemporaneously and using the number of burst patterns.Type: ApplicationFiled: September 13, 2022Publication date: March 14, 2024Inventors: William Yu, Daniele Balluchi, Danilo Caraccio, Thomas T. Tangelder, Jacob S. Robertson, James G. Steele, Joemar Sinipete
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Patent number: 11798622Abstract: Methods, systems, and devices for a refresh operation of a memory cell are described. A memory device may include a plurality of rows of memory cells. Each row of memory cells may undergo a quantity of access operations (e.g., read operations, write operations). During a read operation, a logic state of one or more memory cells may be determined by applying a read pulse having a first polarity. Based on the one or more memory cells storing a particular logic state (e.g., a first logic state), a refresh operation may be performed. During a refresh operation, a refresh pulse having a second polarity (e.g., a different polarity than the first polarity) may be applied to the one or more memory cells.Type: GrantFiled: July 14, 2022Date of Patent: October 24, 2023Assignee: Micron Technology, Inc.Inventors: Joemar Sinipete, John Christopher Sancon, Mingdong Cui
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Publication number: 20220415395Abstract: Methods, systems, and devices for a refresh operation of a memory cell are described. A memory device may include a plurality of rows of memory cells. Each row of memory cells may undergo a quantity of access operations (e.g., read operations, write operations). During a read operation, a logic state of one or more memory cells may be determined by applying a read pulse having a first polarity. Based on the one or more memory cells storing a particular logic state (e.g., a first logic state), a refresh operation may be performed. During a refresh operation, a refresh pulse having a second polarity (e.g., a different polarity than the first polarity) may be applied to the one or more memory cells.Type: ApplicationFiled: July 14, 2022Publication date: December 29, 2022Inventors: Joemar Sinipete, John Christopher Sancon, Mingdong Cui
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Patent number: 11404120Abstract: Methods, systems, and devices for a refresh operation of a memory cell are described. A memory device may include a plurality of rows of memory cells. Each row of memory cells may undergo a quantity of access operations (e.g., read operations, write operations). During a read operation, a logic state of one or more memory cells may be determined by applying a read pulse having a first polarity. Based on the one or more memory cells storing a particular logic state (e.g., a first logic state), a refresh operation may be performed. During a refresh operation, a refresh pulse having a second polarity (e.g., a different polarity than the first polarity) may be applied to the one or more memory cells.Type: GrantFiled: May 13, 2020Date of Patent: August 2, 2022Assignee: Micron Technology, Inc.Inventors: Joemar Sinipete, John Christopher Sancon, Mingdong Cui
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Publication number: 20210358546Abstract: Methods, systems, and devices for a refresh operation of a memory cell are described. A memory device may include a plurality of rows of memory cells. Each row of memory cells may undergo a quantity of access operations (e.g., read operations, write operations). During a read operation, a logic state of one or more memory cells may be determined by applying a read pulse having a first polarity. Based on the one or more memory cells storing a particular logic state (e.g., a first logic state), a refresh operation may be performed. During a refresh operation, a refresh pulse having a second polarity (e.g., a different polarity than the first polarity) may be applied to the one or more memory cells.Type: ApplicationFiled: May 13, 2020Publication date: November 18, 2021Inventors: Joemar Sinipete, John Christopher Sancon, Mingdong Cui
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Patent number: 10665307Abstract: Memory devices include an array of memory cells and circuitry for control and/or access of the array of memory cells, wherein the circuitry is configured to perform a method including applying a first voltage to the access line following a verify of the program operation then electrically floating the access line, connecting the access line to the first input of the operational amplifier, applying a second voltage to a second access line adjacent the access line, applying a reference current to the access line while applying the second voltage to the second access line, applying the reference voltage to the second input of the operational amplifier while applying the second voltage to the second access line, and indicating a fail status of the program operation if current flow to or from the access line exceeds the reference current sinking current from, or sourcing current to, respectively, the first access line.Type: GrantFiled: June 5, 2019Date of Patent: May 26, 2020Assignee: Micron Technology, Inc.Inventors: Jeffrey A. Kessenich, Joemar Sinipete, Chiming Chu, Jason L. Nevill, Kenneth W. Marr, Renato C. Padilla
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Publication number: 20190287634Abstract: Memory devices include an array of memory cells and circuitry for control and/or access of the array of memory cells, wherein the circuitry is configured to perform a method including applying a first voltage to the access line following a verify of the program operation then electrically floating the access line, connecting the access line to the first input of the operational amplifier, applying a second voltage to a second access line adjacent the access line, applying a reference current to the access line while applying the second voltage to the second access line, applying the reference voltage to the second input of the operational amplifier while applying the second voltage to the second access line, and indicating a fail status of the program operation if current flow to or from the access line exceeds the reference current sinking current from, or sourcing current to, respectively, the first access line.Type: ApplicationFiled: June 5, 2019Publication date: September 19, 2019Applicant: MICRON TECHNOLOGY, INC.Inventors: Jeffrey A. Kessenich, Joemar Sinipete, Chiming Chu, Jason L. Nevill, Kenneth W. Marr, Renato C. Padilla
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Patent number: 10366767Abstract: Memory devices include an array of memory cells and circuitry for control and/or access of the array of memory cells, wherein the circuitry is configured to perform a method including applying a particular voltage to an unselected access line of a program operation, sensing a current of a selected access line of the program operation while applying the particular voltage to the unselected access line, indicating a fail status of the program operation if an absolute value of the sensed current of the selected access line is greater than a particular current, and proceeding with the program operation if the absolute value of the sensed current of the selected access line is less than a particular current.Type: GrantFiled: August 25, 2017Date of Patent: July 30, 2019Assignee: Micron Technology, Inc.Inventors: Jeffrey A. Kessenich, Joemar Sinipete, Chiming Chu, Jason L. Nevill, Kenneth W. Marr, Renato C. Padilla
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Publication number: 20170352431Abstract: Memory devices include an array of memory cells and circuitry for control and/or access of the array of memory cells, wherein the circuitry is configured to perform a method including applying a particular voltage to an unselected access line of a program operation, sensing a current of a selected access line of the program operation while applying the particular voltage to the unselected access line, indicating a fail status of the program operation if an absolute value of the sensed current of the selected access line is greater than a particular current, and proceeding with the program operation if the absolute value of the sensed current of the selected access line is less than a particular current.Type: ApplicationFiled: August 25, 2017Publication date: December 7, 2017Applicant: MICRON TECHNOLOGY, INC.Inventors: Jeffrey A. Kessenich, Joemar Sinipete, Chiming Chu, Jason L. Nevill, Kenneth W. Marr, Renato C. Padilla
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Patent number: 9761322Abstract: Methods of operating a memory device having embedded leak checks may mitigate data loss events due to access line defects, and may facilitate improved power consumption characteristics. Such methods might include applying a program pulse to a selected access line coupled to a memory cell selected for programming, verifying whether the selected memory cell has reached a desired data state, bringing the selected access line to a first voltage, applying a second voltage to an unselected access line, applying a reference current to the selected access line, and determining if a current flow between the selected access line and the unselected access line is greater than the reference current.Type: GrantFiled: February 9, 2016Date of Patent: September 12, 2017Assignee: Micron Technology, Inc.Inventors: Jeffery A. Kessenich, Joemar Sinipete, Chiming Chu, Jason L. Nevill, Kenneth W. Marr, Renato C. Padilla
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Publication number: 20160155513Abstract: Methods of operating a memory device having embedded leak checks may mitigate data loss events due to access line defects, and may facilitate improved power consumption characteristics. Such methods might include applying a program pulse to a selected access line coupled to a memory cell selected for programming, verifying whether the selected memory cell has reached a desired data state, bringing the selected access line to a first voltage, applying a second voltage to an unselected access line, applying a reference current to the selected access line, and determining if a current flow between the selected access line and the unselected access line is greater than the reference current.Type: ApplicationFiled: February 9, 2016Publication date: June 2, 2016Applicant: MICRON TECHNOLOGY, INC.Inventors: Jeffery A. Kessenich, Joemar Sinipete, Chiming Chu, Jason L. Nevill, Kenneth W. Marr, Renato C. Padilla
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Patent number: 9281078Abstract: Methods of operating a memory device having embedded leak checks may mitigate data loss events due to access line defects, and may facilitate improved power consumption characteristics. Such methods might include applying a program pulse to a selected access line coupled to a memory cell selected for programming, verifying whether the selected memory cell has reached a desired data state, bringing the selected access line to a first voltage, applying a second voltage to an unselected access line, applying a reference current to the selected access line, and determining if a current flow between the selected access line and the unselected access line is greater than the reference current.Type: GrantFiled: June 12, 2014Date of Patent: March 8, 2016Assignee: Micron Technology, Inc.Inventors: Jeffrey A. Kessenich, Joemar Sinipete, Chiming Chu, Jason L. Nevill, Kenneth W. Marr, Renato C. Padilla
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Publication number: 20150364213Abstract: Methods of operating a memory device having embedded leak checks may mitigate data loss events due to access line defects, and may facilitate improved power consumption characteristics. Such methods might include applying a program pulse to a selected access line coupled to a memory cell selected for programming, verifying whether the selected memory cell has reached a desired data state, bringing the selected access line to a first voltage, applying a second voltage to an unselected access line, applying a reference current to the selected access line, and determining if a current flow between the selected access line and the unselected access line is greater than the reference current.Type: ApplicationFiled: June 12, 2014Publication date: December 17, 2015Applicant: Micron Technology, Inc.Inventors: Jeffrey A. Kessenich, Joemar Sinipete, Chiming Chu, Jason L. Nevill, Kenneth W. Marr, Renato C. Padilla
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Patent number: 8094508Abstract: A memory block of a memory device is tested by programming a plurality of pages of the memory block, passing the memory block if a number of pages, each programmed in a first programming time, is greater than or equal to a first predetermined number and a number of pages, each programmed in a second programming time, is less than or equal to a second predetermined number, and failing the memory block if a programming time of any one of the pages exceeds a predetermined programming time or if the number of pages programmed in the first programming time is less than the first predetermined number or if the number of pages programmed in the second programming time exceeds the second predetermined number.Type: GrantFiled: July 27, 2009Date of Patent: January 10, 2012Assignee: Micron Technology, Inc.Inventors: Scott N. Gatzemeier, Joemar Sinipete, Nevil Gajera, Mark Hawes
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Publication number: 20090290441Abstract: A memory block of a memory device is tested by programming a plurality of pages of the memory block, passing the memory block if a number of pages, each programmed in a first programming time, is greater than or equal to a first predetermined number and a number of pages, each programmed in a second programming time, is less than or equal to a second predetermined number, and failing the memory block if a programming time of any one of the pages exceeds a predetermined programming time or if the number of pages programmed in the first programming time is less than the first predetermined number or if the number of pages programmed in the second programming time exceeds the second predetermined number.Type: ApplicationFiled: July 27, 2009Publication date: November 26, 2009Inventors: Scott N. Gatzemeier, Joemar Sinipete, Nevil Gajera, Mark Hawes
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Patent number: 7567472Abstract: A memory device is tested by programming a plurality of pages of a memory block of the memory device, determining a programming time for each page, determining a total programming time for the memory block, passing the memory block if the total programming time for the memory block is less than or equal to a first predetermined time, and failing the memory block if the total programming time for the memory block exceeds the first predetermined time or the programming time for any one of the pages exceeds a second predetermined time.Type: GrantFiled: April 12, 2006Date of Patent: July 28, 2009Assignee: Micron Technology, Inc.Inventors: Scott N. Gatzemeier, Joemar Sinipete, Nevil Gajera, Mark Hawes
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Publication number: 20070266276Abstract: A memory device is tested by programming a plurality of pages of a memory block of the memory device, determining a programming time for each page, determining a total programming time for the memory block, passing the memory block if the total programming time for the memory block is less than or equal to a first predetermined time, and failing the memory block if the total programming time for the memory block exceeds the first predetermined time or the programming time for any one of the pages exceeds a second predetermined time.Type: ApplicationFiled: April 12, 2006Publication date: November 15, 2007Inventors: Scott Gatzemeier, Joemar Sinipete, Nevil Gajera, Mark Hawes
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Publication number: 20070225928Abstract: Methods and structures are described to provide trims for die on a wafer. The trims are set on a die-by-die basis instead of a wafer basis. Accordingly, the individual die are more finely tuned and more die operate at the target specifications so that yield is increased. In an embodiment, the odd and even blocks of each non volatile memory die are erased and then programmed to test the program time. Statistical analysis of the tested program times is performed. Based on this analysis the trim values are determined and programmed into the die. Accordingly, each die on a wafer has its individual trim settings.Type: ApplicationFiled: March 23, 2006Publication date: September 27, 2007Inventors: Scott Gatzemeier, Joemar Sinipete, Robert Ringhofer, Nevil Gajera, Mark Hawes