Abstract: Determining simulation test coverage for a design of an electronic circuit, where graph-based verification tools are used to verify functional correctness of said design. A test coverage is determined from specified coverage points, and hardware test coverage is measured based on the occurrence of selected events. A specification for simulation test scenarios, and a hardware design language specification for the design comprising hardware events are provided. A list of event groups belonging to one simulation test scenario is created. For each group a temporal property coverage checker in the simulation model is generated that comprises a switch to enable or disable it.

Abstract: Disclosed aspects relate to a first-in-first-out (FIFO) buffer. The FIFO buffer may include an input interface to receive a set of data payloads. The FIFO buffer may include a set of buffer entry elements to store the set of data payloads. The FIFO buffer may include a set of status indicators to indicate a set of statuses of the set of buffer entry elements with respect to the set of data payloads. The FIFO buffer may include an output interface for release of the set of data payloads.

Abstract: Disclosed aspects relate to controlling an electronic circuit having multiple units with at least one signal input each. A set of signal resources is determined by tracing back a dependency tree for each unit signal input until an endpoint representing a signal resource is reached. For each signal resource in the set a resource manager may be provided in dependence of its signal type. That resource manager may be assigned a set of signal inputs comprising each signal input in the circuit which was traced back to its respective signal resource. The resource manager is configured for controlling the signal resource. A control device may be provided to receive technical implementation requirements for one or more of the resource managers, detect conflicting requirements received for the one or more resource managers, and enable or disable one or more of the resource managers in response to the detected conflicting requirements.

Abstract: Disclosed aspects relate to controlling an electronic circuit having multiple units with at least one signal input each. A set of signal resources is determined by tracing back a dependency tree for each unit signal input until an endpoint representing a signal resource is reached. For each signal resource in the set a resource manager may be provided in dependence of its signal type. That resource manager may be assigned a set of signal inputs comprising each signal input in the circuit which was traced back to its respective signal resource. The resource manager is configured for controlling the signal resource. A control device may be provided to receive technical implementation requirements for one or more of the resource managers, detect conflicting requirements received for the one or more resource managers, and enable or disable one or more of the resource managers in response to the detected conflicting requirements.

Abstract: The invention relates to a method for verifying a design of an electronic circuit. The electronic circuit comprises at least one register including one or more parts. After receiving specification information of said register, a register monitor module is automatically created based on said received specification information. The register monitor module comprises a scoreboard for each part of the register. Said scoreboard comprises an expected data value queue for receiving expected data values, an actual data value queue for receiving actual data values. Furthermore, the register monitor module provides a matching strategy for comparing expected data values with actual data values. Expected data values and actual data values are compared for each scoreboard based on the matching strategy and an error indication is generated if the result of the comparison step does not fulfill the requirements specified in the matching strategy.

Abstract: Disclosed aspects relate to controlling an electronic circuit having multiple units with at least one signal input each. A set of signal resources is determined by tracing back a dependency tree for each unit signal input until an endpoint representing a signal resource is reached. For each signal resource in the set a resource manager may be provided in dependence of its signal type. That resource manager may be assigned a set of signal inputs comprising each signal input in the circuit which was traced back to its respective signal resource. The resource manager is configured for controlling the signal resource. A control device may be provided to receive technical implementation requirements for one or more of the resource managers, detect conflicting requirements received for the one or more resource managers, and enable or disable one or more of the resource managers in response to the detected conflicting requirements.

Abstract: Disclosed aspects relate to controlling an electronic circuit having multiple units with at least one signal input each. A set of signal resources is determined by tracing back a dependency tree for each unit signal input until an endpoint representing a signal resource is reached. For each signal resource in the set a resource manager may be provided in dependence of its signal type. That resource manager may be assigned a set of signal inputs comprising each signal input in the circuit which was traced back to its respective signal resource. The resource manager is configured for controlling the signal resource. A control device may be provided to receive technical implementation requirements for one or more of the resource managers, detect conflicting requirements received for the one or more resource managers, and enable or disable one or more of the resource managers in response to the detected conflicting requirements.

Abstract: Disclosed aspects relate to a first-in-first-out (FIFO) buffer. The FIFO buffer may include an input interface to receive a set of data payloads. The FIFO buffer may include a set of buffer entry elements to store the set of data payloads. The FIFO buffer may include a set of status indicators to indicate a set of statuses of the set of buffer entry elements with respect to the set of data payloads. The FIFO buffer may include an output interface for release of the set of data payloads.

Abstract: Disclosed aspects relate to a first-in-first-out (FIFO) buffer. The FIFO buffer may include an input interface to receive a set of data payloads. The FIFO buffer may include a set of buffer entry elements to store the set of data payloads. The FIFO buffer may include a set of status indicators to indicate a set of statuses of the set of buffer entry elements with respect to the set of data payloads. The FIFO buffer may include an output interface for release of the set of data payloads.

Abstract: The invention relates to a method for verifying a design of an electronic circuit. The electronic circuit comprises at least one register including one or more parts. After receiving specification information of said register, a register monitor module is automatically created based on said received specification information. The register monitor module comprises a scoreboard for each part of the register. Said scoreboard comprises an expected data value queue for receiving expected data values, an actual data value queue for receiving actual data values. Furthermore, the register monitor module provides a matching strategy for comparing expected data values with actual data values. Expected data values and actual data values are compared for each scoreboard based on the matching strategy and an error indication is generated if the result of the comparison step does not fulfil the requirements specified in the matching strategy.