Abstract: A method and apparatus for the production of a test-compatible, largely defect-tolerant configuration of redundantly implemented, systolic VLSI systems. The method and apparatus for the configuration of redundantly implemented, systolic VLSI systems meets the conditions of defect-tolerance, test-compatibility and minimum hardware requirement. For this purpose, every module of the multi-dimensional systolic VLSI system has control logic allocated to it which controls A, B and C switches for the appertaining module. It is possible with the use of these switches to bridge a maximum of up to two faulty modules per row and one faulty module per column. A configuration algorithm provides a determination as to whether the established VLSI system is in the position to be able to execute the desired arithmetic operations.