Abstract: Driving address translations in a microprocessor system by sending a rejected Lx+1 cache request from a first set of caches of a first level Lx to a central request unit, transferring an Lx+1 cache request having a translation of a virtual address into a physical address stored in a first buffer, from the central request unit to the at least one Lx+1 cache, and keeping an Lx+1 cache request lacking a translation of a virtual address into a physical address stored in the first buffer, pending in the central request unit.

Abstract: Driving address translations in a microprocessor system by sending a rejected Lx+1 cache request from a first set of caches of a first level Lx to a central request unit, transferring an Lx+1 cache request having a translation of a virtual address into a physical address stored in a first buffer, from the central request unit to the at least one Lx+1 cache, and keeping an Lx+1 cache request lacking a translation of a virtual address into a physical address stored in the first buffer, pending in the central request unit.

Abstract: Generating instructions, in particular for mailbox verification in a simulation environment. A sequence of instructions is received, as well as selection data representative of a plurality of commands including a special command. Repeatedly selecting one of the plurality of commands and outputting an instruction based on the selected command. The outputting of an instruction includes outputting a next instruction in the sequence of instructions if the selected command is the special command, and outputting an instruction associated with the command if the selected command is not the special command.

Abstract: Generating instructions, in particular for mailbox verification in a simulation environment. A sequence of instructions is received, as well as selection data representative of a plurality of commands including a special command. Repeatedly selecting one of the plurality of commands and outputting an instruction based on the selected command. The outputting of an instruction includes outputting a next instruction in the sequence of instructions if the selected command is the special command, and outputting an instruction associated with the command if the selected command is not the special command.

Abstract: Generating instructions, in particular for mailbox verification in a simulation environment. A sequence of instructions is received, as well as selection data representative of a plurality of commands including a special command. Repeatedly selecting one of the plurality of commands and outputting an instruction based on the selected command. The outputting of an instruction includes outputting a next instruction in the sequence of instructions if the selected command is the special command, and outputting an instruction associated with the command if the selected command is not the special command.

Abstract: Generating instructions, in particular for mailbox verification in a simulation environment. A sequence of instructions is received, as well as selection data representative of a plurality of commands including a special command. Repeatedly selecting one of the plurality of commands and outputting an instruction based on the selected command. The outputting of an instruction includes outputting a next instruction in the sequence of instructions if the selected command is the special command, and outputting an instruction associated with the command if the selected command is not the special command.

Abstract: Generating instructions, in particular for mailbox verification in a simulation environment. A sequence of instructions is received, as well as selection data representative of a plurality of commands including a special command. Repeatedly selecting one of the plurality of commands and outputting an instruction based on the selected command. The outputting of an instruction includes outputting a next instruction in the sequence of instructions if the selected command is the special command, and outputting an instruction associated with the command if the selected command is not the special command.

Abstract: A translation lookaside buffer coherency unit with Emulated Purge (TCUEP) translates a first virtual address for a first instruction into a first physical address. The TCUEP detects a multi-processor coherency operation that will cause hit suppression for certain entries in a TLB and purging of certain entries in the TLB. The TCUEP translates a second virtual address for a second instruction into a second physical address and stores the second physical address in a second entry in the TLB. The TCUEP configures a second marker in the second entry to indicate that the hit suppression is not allowed for the second entry, and that the purging is not allowed for the second entry. The TCUEP receives a first address translation request that indicates a hit in the second entry. The TCUEP resolves the first address translation request by returning the second physical address.

Abstract: A translation lookaside buffer coherency unit with Emulated Purge (TCUEP) translates a first virtual address for a first instruction into a first physical address. The TCUEP detects a multi-processor coherency operation that will cause hit suppression for certain entries in a TLB and purging of certain entries in the TLB. The TCUEP translates a second virtual address for a second instruction into a second physical address and stores the second physical address in a second entry in the TLB. The TCUEP configures a second marker in the second entry to indicate that the hit suppression is not allowed for the second entry, and that the purging is not allowed for the second entry. The TCUEP receives a first address translation request that indicates a hit in the second entry. The TCUEP resolves the first address translation request by returning the second physical address.

Abstract: The present invention relates to a method for generating coverage data for a switch frequency of HDL or VHDL signals with the steps of providing a HDL or VHDL hardware description model within a register transfer level, providing a filtering algorithm or filtering rules for signals occurring in the HDL or VHDL hardware description model, extracting signals from the HDL or VHDL hardware description model according to said filtering algorithm or filtering rules in order to get relevant signals, performing a simulation process of the HDL or VHDL hardware description model, performing a checking routine for the relevant signals in every cycle and storing and/or cumulating the relevant signals in a data base. Further the present invention relates to a corresponding system.

Abstract: A translation lookaside buffer coherency unit with Emulated Purge (TCUEP) translates a first virtual address for a first instruction into a first physical address. The TCUEP detects a multi-processor coherency operation that will cause hit suppression for certain entries in a TLB and purging of certain entries in the TLB. The TCUEP translates a second virtual address for a second instruction into a second physical address and stores the second physical address in a second entry in the TLB. The TCUEP configures a second marker in the second entry to indicate that the hit suppression is not allowed for the second entry, and that the purging is not allowed for the second entry. The TCUEP receives a first address translation request that indicates a hit in the second entry. The TCUEP resolves the first address translation request by returning the second physical address.

Abstract: Some embodiments include a method that can store a first physical address in a first entry in a translation lookaside buffer (TLB). The method can configure a first marker in the first entry in the TLB to indicate that hit suppression is allowed for the first entry. The method can detect a multi-processor coherency operation that will cause hit suppression for certain entries in a TLB, and cause purging of certain entries in the TLB. The method can translate a second virtual address for a second instruction into a second physical address. The method can store the second physical address in a second entry. The method can configure a second marker in the second entry in the TLB to indicate that the hit suppression is not allowed for the second entry in the TLB, and that the purging is not allowed for the second entry in the TLB.

Abstract: A computer processor receives a plurality of execution items corresponding to a computer process. The computer processor allocates a first memory portion corresponding to a first stack, wherein the first stack corresponds to a first class of execution items. The computer processor allocates a second memory portion corresponding to a second stack, wherein the second stack corresponds to a second class of execution items. The computer processor identifies a first execution item of the plurality of execution items and determining a class corresponding to the first execution item.

Abstract: A computer processor receives a plurality of execution items corresponding to a computer process. The computer processor allocates a first memory portion corresponding to a first stack, wherein the first stack corresponds to a first class of execution items. The computer processor allocates a second memory portion corresponding to a second stack, wherein the second stack corresponds to a second class of execution items. The computer processor identifies a first execution item of the plurality of execution items and determining a class corresponding to the first execution item.

Abstract: A simulation environment verifies processor-sparing functions in a simulated processor core. The simulation environment executes a first simulation for a simulated processor core. During the simulation, the simulation environment creates a simulation model dump file. At a later point in time, the simulation environment executes a second simulation for the simulated processor core. The simulation environment saves the state of the simulated processor core. The simulation environment then replaces the state of the simulated processor core by loading the previously created simulation model dump file. The simulation environment then sets the state of the simulated processor core to execute processor-sparing code and resumes the second simulation.

Abstract: A translation lookaside buffer coherency unit with Emulated Purge (TCUEP) fetches first instructions for execution in a multi-processor system. The TCUEP associates a first instruction timestamp with each of the first instructions. The TCUEP receives a multi-processor coherency operation and increments the first timestamp value in a master-tag register to form a second timestamp value after receiving the multi-processor coherency operation. The TCUEP fetches, by an instruction fetch unit in the first microprocessor, second instructions for execution in the multiprocessor system. The TCUEP associates a second instruction timestamp with each of the second instructions. The TCUEP enables an emulated purge mechanism to suppress hits in the translation lookaside buffers for the second instructions. The TCUEP after determining the first instructions are complete, purges entries in the translation lookaside buffers and disables the emulated purge mechanism.

Abstract: A translation lookaside buffer coherency unit with Emulated Purge (TCUEP) fetches first instructions for execution in a multi-processor system. The TCUEP associates a first instruction timestamp with each of the first instructions. The TCUEP receives a multi-processor coherency operation and increments the first timestamp value in a master-tag register to form a second timestamp value after receiving the multi-processor coherency operation. The TCUEP fetches, by an instruction fetch unit in the first microprocessor, second instructions for execution in the multiprocessor system. The TCUEP associates a second instruction timestamp with each of the second instructions. The TCUEP enables an emulated purge mechanism to suppress hits in the translation lookaside buffers for the second instructions. The TCUEP after determining the first instructions are complete, purges entries in the translation lookaside buffers and disables the emulated purge mechanism.

Abstract: A computer processor receives a plurality of execution items corresponding to a computer process. The computer processor allocates a first memory portion corresponding to a first stack, wherein the first stack corresponds to a first class of execution items. The computer processor allocates a second memory portion corresponding to a second stack, wherein the second stack corresponds to a second class of execution items. The computer processor identifies a first execution item of the plurality of execution items and determining a class corresponding to the first execution item.

Abstract: A computer processor receives a plurality of execution items corresponding to a computer process. The computer processor allocates a first memory portion corresponding to a first stack, wherein the first stack corresponds to a first class of execution items. The computer processor allocates a second memory portion corresponding to a second stack, wherein the second stack corresponds to a second class of execution items. The computer processor identifies a first execution item of the plurality of execution items and determining a class corresponding to the first execution item.

Abstract: A simulation environment verifies processor-sparing functions in a simulated processor core. The simulation environment executes a first simulation for a simulated processor core. During the simulation, the simulation environment creates a simulation model dump file. At a later point in time, the simulation environment executes a second simulation for the simulated processor core. The simulation environment saves the state of the simulated processor core. The simulation environment then replaces the state of the simulated processor core by loading the previously created simulation model dump file. The simulation environment then sets the state of the simulated processor core to execute processor-sparing code and resumes the second simulation.