Abstract: The invention relates to a device for positioning a semiconductor die in a wafer prober, the device comprising a carrier plate and a clamp on a front surface of the carrier plate, the dimensions of the carrier plate matching a standard geometry required by the wafer prober for receiving a semiconductor wafer to be probed by the wafer prober, the clamp being reversibly movable against a force of an elastic element between an open position and a closed position, the clamp being adapted for fixing the die on the carrier plate in the closed position and for releasing the die in the open position.

Abstract: The invention relates to a device for positioning a semiconductor die in a wafer prober, the device comprising a carrier plate and a clamp on a front surface of the carrier plate, the dimensions of the carrier plate matching a standard geometry required by the wafer prober for receiving a semiconductor wafer to be probed by the wafer prober, the clamp being reversibly movable against a force of an elastic element between an open position and a closed position, the clamp being adapted for fixing the die on the carrier plate in the closed position and for releasing the die in the open position.

Abstract: A method and system for efficiently coding test pattern for ICs in scan design and build-in linear feedback shift register (LFSR) for pseudo-random pattern generation. In an initialization procedure, a novel LFSR logic model is generated and integrated into the system for test data generation and test vector compression. In a test data generation procedure, test vectors are specified and compressed using the LFSR logic model. Every single one of the test vectors is compressed independently from the others. The result, however, may be presented all at once and subsequently provided to the user or another system for further processing or implementing in an integrated circuit to be tested. According to the present invention a test vector containing 0/1-values for, e.g., up to 500.000 shift registers and having, e.g., about 50 so called care-bits can be compressed to a compact pattern code of the number of care-bits, i.e., 50 bits for the example of 50 care-bits.

Abstract: A plurality of pseudo random bit-pattern generators (PRPGs), advantageously linear feedback shift registers (LFSRs), having predetermined lengths and individual different tap locations for providing a respective sequence of pseudorandom bit-patterns. An output from a predetermined respective tap location at each LFSR is fed to a common OR-gate, a selected subset of the LFSRs are initialized with all bit storing locations to “0” in order to generate a respective permanent “0”-bit sequence, and the output of the OR-gate is used for reading the weighted or flat random bit output-pattern thereof. By controlling the number of zero-set LFSRs—a subset of the LFSRs—the weight of the generated output-pattern can be controlled.

Abstract: A method and system for efficiently coding test pattern for ICs in scan design and build-in linear feedback shift register (LFSR) for pseudo-random pattern generation. In an initialization procedure, a novel LFSR logic model is generated and integrated into the system for test data generation and test vector compression. In a test data generation procedure, test vectors are specified and compressed using the LFSR logic model. Every single one of the test vectors is compressed independently from the others. The result, however, may be presented all at once and subsequently provided to the user or another system for further processing or implementing in an integrated circuit to be tested. According to the present invention a test vector containing 0/1-values for, e.g., up to 500.000 shift registers and having, e.g., about 50 so called care-bits can be compressed to a compact pattern code of the number of care-bits, i.e., 50 bits for the example of 50 care-bits.

Abstract: A plurality of pseudo random bit-pattern generators (PRPG), advantageously Linear Feedback Shift Registers (LFSRs), having a predetermined length and individual different tap locations for providing a respective sequence of pseudorandom bit-patterns. An output from a predetermined respective tap location at each LSR is fed to a common OR-gate, a selected subset of said LFSRs are initialized with all bit storing locations to “0” in order to generate a respective permanent “0”-bit sequence, and the output of said OR-gate is used for reading the weighted or flat random bit output-pattern thereof. By controlling the number of zero-set LFSRs—a subset of said LFSRs—the weight of the generated output-pattern can be controlled.