Abstract: A device for generating clock signals for use with a plurality of DDR memory devices on a dual in-line memory module (DIMM) board is provided that has a data buffer for buffering data. A clock divider divides a first clock signal (CLK1) having a first clock frequency to generate a second clock signal (CLK20) having a second clock frequency which is an integer multiple of the first clock frequency. A shift register (SH) receives the second clock signal as a data input signal, and comprises a plurality flip-flops having clock inputs coupled to receive the first clock signal (CLK1), and further coupled so that the data output of a preceding flip-flop is coupled to be the data input of a following flip-flop. The second clock signal is shifted through the shift register (SH) in response to the first clock signal (CLK1) to generate a plurality of shifted clock signals (CLK 21, . . . , CLK32) at respective data outputs of the plurality of flip-flops.

Abstract: The present invention relates to an electronic transmitter for serially transmitting bit sequences. The electronic transmitter includes a detection device 10 and a transmitting device 12. The detection device 10 is adapted to detect a predefined bit sequence for transmittal. The predefined bit sequence is susceptible to inter-symbol-interference. The transmitting device 12 is adapted to transmit serially the detected predefined bit sequence in such a way, that a duration for transmittal of a particular bit in said predefined bit sequence is longer than a duration of transmittal of remaining bits in said predefined bit sequence.

Abstract: A device for generating clock signals for use with a plurality of DDR memory devices on a dual in-line memory module (DIMM) board is provided that has a data buffer for buffering data. A clock divider divides a first clock signal (CLK1) having a first clock frequency to generate a second clock signal (CLK20) having a second clock frequency which is an integer multiple of the first clock frequency. A shift register (SH) receives the second clock signal as a data input signal, and comprises a plurality flip-flops having clock inputs coupled to receive the first clock signal (CLK1), and further coupled so that the data output of a preceding flip-flop is coupled to be the data input of a following flip-flop. The second clock signal is shifted through the shift register (SH) in response to the first clock signal (CLK1) to generate a plurality of shifted clock signals (CLK 21, . . . , CLK32) at respective data outputs of the plurality of flip-flops.

Abstract: Digital data are recovered from a clocked serial input signal. The input signal is sampled with a sampling clock signal supplied by a first phase interpolator to obtain a sampled digital signal. The first phase interpolator is controlled with a voting circuit to adjust the phase of the sampling clock relative to the eye in the eye-diagram of the input signal. The first phase interpolator has signal inputs connected to signal outputs of a voltage controlled oscillator in a phase-locked loop circuit that has a reference signal input to which the reference clock signal is applied. The sampled digital signal is written to a single-bit FIFO buffer with a write clock signal that has the same timing as the sampling clock. A filtered output signal is read from the FIFO buffer with a read clock signal supplied by a second phase interpolator that has signal inputs connected to the signal outputs of the voltage controlled oscillator in the phase-locked loop.

Abstract: A data synchronization arrangement is provided for exchanging clocked data between different clock domains running at the same clock frequency but at an arbitrary relative phase shift. An input data stream synchronized in the first clock domain is written into respective locations of a buffer memory through a write select multiplexer under control of a write select shift register clocked by the first domain clock. An output data stream synchronized in the second clock domain is read from the respective locations of the buffer memory through a real select multiplexer under control of a read select shift register clocked by the second domain clock. A bit synchronization circuit is provided for loading the read select shift register with a bit pattern that has a relative offset relative to the bit pattern of the write select shift register, to correlate for the difference in clock phases.

Abstract: Digital data are recovered from a clocked serial input signal. The input signal is sampled with a sampling clock signal supplied by a first phase interpolator to obtain a sampled digital signal. The first phase interpolator is controlled with a voting circuit to adjust the phase of the sampling clock relative to the eye in the eye-diagram of the input signal. The first phase interpolator has signal inputs connected to signal outputs of a voltage controlled oscillator in a phase-locked loop circuit that has a reference signal input to which the reference clock signal is applied. The sampled digital signal is written to a single-bit FIFO buffer with a write clock signal that has the same timing as the sampling clock. A filtered output signal is read from the FIFO buffer with a read clock signal supplied by a second phase interpolator that has signal inputs connected to the signal outputs of the voltage controlled oscillator in the phase-locked loop.

Abstract: The present invention relates to an electronic transmitter for serially transmitting bit sequences. The electronic transmitter includes a detection device 10 and a transmitting device 12. The detection device 10 is adapted to detect a predefined bit sequence for transmittal. The predefined bit sequence is susceptible to inter-symbol-interference. The transmitting device 12 is adapted to transmit serially the detected predefined bit sequence in such a way, that a duration for transmittal of a particular bit in said predefined bit sequence is longer than a duration of transmittal of remaining bits in said predefined bit sequence.

Abstract: In a high-speed serial transmission system (10) comprising a transmitter (12), a transmission line (14) and a receiver (16), the transmitter (12) includes a bit-stream generator (18) for generating a predetermined pseudo random bit sequence (PRBS), and a controllable phase distortion circuit (20) having an input (24) connected to the bit-stream generator (18) and a signal output (26) connected to the transmission line (14).

Abstract: A data synchronization arrangement is provided that is fail-safe at high speed and low power consumption, for exchanging clocked data between different clock domains running in a digital processing equipment at the same clock frequency but at an arbitrary relative phase shift. A register arrangement has a predetermined number of parallel registers, each register having a data input, a write clock input, a read clock input and a data output. A write select multiplexer has an input receiving a write clock signal from a first clock domain, one clock output for each of the parallel registers and connected to a write clock input of a respective register, and one write select input for each clock output. A read select multiplexer has an input receiving a read clock signal from a second clock domain, one clock output for each of the parallel registers and connected to a read clock input of a respective register, and one read select input for each clock output.

Abstract: In the proposed method of sampling data that are related to a clock signal, a three test samples are taken from the same data at positions in time spaced from each other by fixed delays by shifting the clock signal in time with respect to the data until the test samples taken from the same data have an identical value. A shifted clock signal is used to take validated samples of the data. Since the clock is shifted in time in relation to the data so that all test samples have an identical value, that value is the true value of a datum sampled within a period of time from the moment of the first test sample to the moment of the last test sample, and a validated data sample is obtained.

Abstract: A data synchronization arrangement is provided that is fail-safe at high speed and low power consumption, for exchanging clocked data between different clock domains running in a digital processing equipment at the same clock frequency but at an arbitrary relative phase shift. A register arrangement has a predetermined number of parallel registers, each register having a data input, a write clock input, a read clock input and a data output. A write select multiplexer has an input receiving a write clock signal from a first clock domain, one clock output for each of the parallel registers and connected to a write clock input of a respective register, and one write select input for each clock output. A read select multiplexer has an input receiving a read clock signal from a second clock domain, one clock output for each of the parallel registers and connected to a read clock input of a respective register, and one read select input for each clock output.

Abstract: A data synchronization arrangement is provided that is fail-safe and allows high-speed operation. Clocked data are exchanged between different clock domains running in a digital processing equipment at the same clock frequency but at an arbitrary relative phase shift. The data synchronization arrangement comprises a buffer memory with a predetermined limited number of memory locations each of which has a data write port and a data read port. A write select multiplexer has a data input receiving an input data stream synchronized with the clock from a first clock domain, one data output for each of said memory locations and connected to a respective data write port, and one write select input for each data output. A read select multiplexer has one data input for each of the memory locations and connected to a respective data read port, one read select input for each data input, and a data output supplying an output data stream synchronized with the clock from a second clock domain.

Abstract: A device for generating clock signals for use with a plurality of DDR memory devices on a dual in-line memory module (DIMM) board is provided that has a data buffer for buffering data. A clock divider divides a first clock signal (CLK1) having a first clock frequency to generate a second clock signal (CLK20) having a second clock frequency which is an integer multiple of the first clock frequency. A shift register (SH) receives the second clock signal as a data input signal, and comprises a plurality flip-flops having clock inputs coupled to receive the first clock signal (CLK1), and further coupled so that the data output of a preceding flip-flop is coupled to be the data input of a following flip-flop. The second clock signal is shifted through the shift register (SH) in response to the first clock signal (CLK1) to generate a plurality of shifted clock signals (CLK 21, . . . , CLK32) at respective data outputs of the plurality of flip-flops.