Patents by Inventor Joerg Haberecht
Joerg Haberecht has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240200226Abstract: A process produces semiconductor wafers with an epitaxial layer deposited from a gas phase. The process includes: removing material deposited in a deposition chamber from preceding coating operations by etching the deposition chamber; carrying out coating operations in succession, which each entail depositing an epitaxial layer on a substrate wafer in the deposition chamber, including passing a first gas stream of first deposition gas over the substrate wafer to form a semiconductor wafer with the epitaxial layer; and before/after each coating operation, passing a second gas stream of a second deposition gas to an edge region of the substrate/semiconductor wafer. A change is made to a process parameter whose effect is that, through the passing of the second deposition gas, deposition of material in the edge region increases as a function of a number of coating operations carried out since the removal of material from the deposition chamber.Type: ApplicationFiled: April 4, 2022Publication date: June 20, 2024Inventors: Ronny Hengst, Joerg Haberecht
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Patent number: 11982015Abstract: Variations in wafer thickness due to non-uniform CVD depositions at angular positions corresponding to crystallographic orientation of the wafer are reduced by providing a ring below the susceptor having inward projections at azimuthal positions which reduce radiant heat impinging upon the wafer at positions of increased deposition.Type: GrantFiled: April 29, 2020Date of Patent: May 14, 2024Assignee: SILTRONIC AGInventors: Joerg Haberecht, Stephan Heinrich, Reinhard Schauer, Rene Stein
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Patent number: 11578424Abstract: A semiconductor wafer comprises a substrate wafer of monocrystalline silicon and a dopant-containing epitaxial layer of monocrystalline silicon atop the substrate wafer, wherein a non-uniformity of the thickness of the epitaxial layer is not more than 0.5% and a non-uniformity of the specific electrical resistance of the epitaxial layer is not more than 2%.Type: GrantFiled: July 12, 2018Date of Patent: February 14, 2023Assignee: SILTRONIC AGInventors: Reinhard Schauer, Joerg Haberecht
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Patent number: 11538683Abstract: A method deposits an epitaxial layer on a front side of a semiconductor wafer having monocrystalline material. The method includes: providing the semiconductor wafer; arranging the semiconductor wafer on a susceptor; heating the semiconductor wafer to a deposition temperature using thermal radiation directed to the front side and to the rear side of the semiconductor wafer; conducting a deposition gas over the front side of the semiconductor wafer; and selectively reducing an intensity of a portion of the thermal radiation that is directed to the rear side of the semiconductor wafer, as a result of which first partial regions at an edge of the semiconductor wafer, in the first partial regions a growth rate of the epitaxial layer is greater than in adjacent second partial regions given uniform temperature of the semiconductor wafer owing to an orientation of the monocrystalline material, are heated more weakly.Type: GrantFiled: November 28, 2018Date of Patent: December 27, 2022Assignee: SILTRONIC AGInventors: Joerg Haberecht, Rene Stein, Stephan Heinrich
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Publication number: 20220267926Abstract: Variations in wafer thickness due to non-uniform CVD depositions at angular positions corresponding to crystallographic orientation of the wafer are reduced by providing a ring below the susceptor having inward projections at azimuthal positions which reduce radiant heat impinging upon the wafer at positions of increased deposition.Type: ApplicationFiled: April 29, 2020Publication date: August 25, 2022Applicant: SILTRONIC AGInventors: Joerg HABERECHT, Stephan HEINRICH, Reinhard SCHAUER, Rene STEIN
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Patent number: 10982324Abstract: Coated semiconductor wafers are produced by introducing a process gas through first gas inlet openings along a first flow direction into a reactor chamber and over a substrate wafer of semiconductor material lying on a susceptor in order to deposit a layer on the substrate wafer, whereby material derived from the process gas precipitates on a preheat ring arranged around the susceptor; extracting the coated substrate wafer from the reactor chamber; and subsequently removing material precipitate from the preheat ring by introducing an etching gas through the first gas inlet openings into the reactor chamber along the first flow direction over the preheat ring and also through second gas inlet openings between which the first gas inlet openings are arranged, along further flow directions which intersect with the first flow direction.Type: GrantFiled: June 13, 2017Date of Patent: April 20, 2021Assignee: Siltronic AGInventor: Joerg Haberecht
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Publication number: 20210087705Abstract: A semiconductor wafer comprises a substrate wafer of monocrystalline silicon and a dopant-containing epitaxial layer of monocrystalline silicon atop the substrate wafer, wherein a non-uniformity of the thickness of the epitaxial layer is not more than 0.5% and a non-uniformity of the specific electrical resistance of the epitaxial layer is not more than 2%.Type: ApplicationFiled: July 12, 2018Publication date: March 25, 2021Applicant: SILTRONIC AGInventors: Reinhard SCHAUER, Joerg HABERECHT
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Patent number: 10865499Abstract: A susceptor for holding a semiconductor wafer during the deposition of an epitaxial layer on a front side of the semiconductor wafer, has a susceptor ring and a susceptor base, and recesses below the susceptor ring in the susceptor base which are arranged in a manner distributed rotationally symmetrically. The radial width of the recesses is greater than the radial width of the susceptor such that the susceptor ring does not completely cover the recesses.Type: GrantFiled: May 31, 2017Date of Patent: December 15, 2020Assignee: SILTRONIC AGInventor: Joerg Haberecht
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Publication number: 20200318234Abstract: Coated semiconductor wafers are produced by introducing a process gas through first gas inlet openings along a first flow direction into a reactor chamber and over a substrate wafer of semiconductor material lying on a susceptor in order to deposit a layer on the substrate wafer, whereby material derived from the process gas precipitates on a preheat ring arranged around the susceptor; extracting the coated substrate wafer from the reactor chamber; and subsequently removing material precipitate from the preheat ring by introducing an etching gas through the first gas inlet openings into the reactor chamber along the first flow direction over the preheat ring and also through second gas inlet openings between which the first gas inlet openings are arranged, along further flow directions which intersect with the first flow direction.Type: ApplicationFiled: June 13, 2017Publication date: October 8, 2020Applicant: SILTRONIC AGInventor: Joerg HABERECHT
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Publication number: 20200294794Abstract: A method deposits an epitaxial layer on a front side of a semiconductor wafer having monocrystalline material. The method includes: providing the semiconductor wafer; arranging the semiconductor wafer on a susceptor; heating the semiconductor wafer to a deposition temperature using thermal radiation directed to the front side and to the rear side of the semiconductor wafer; conducting a deposition gas over the front side of the semiconductor wafer; and selectively reducing an intensity of a portion of the thermal radiation that is directed to the rear side of the semiconductor wafer, as a result of which first partial regions at an edge of the semiconductor wafer, in the first partial regions a growth rate of the epitaxial layer is greater than in adjacent second partial regions given uniform temperature of the semiconductor wafer owing to an orientation of the monocrystalline material, are heated more weakly.Type: ApplicationFiled: November 28, 2018Publication date: September 17, 2020Inventors: Joerg Haberecht, Rene Stein, Stephan Heinrich
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Publication number: 20190106809Abstract: A susceptor for holding a semiconductor wafer during the deposition of an epitaxial layer on a front side of the semiconductor wafer, has a susceptor ring and a susceptor base, and recesses below the susceptor ring in the susceptor base which are arranged in a manner distributed rotationally symmetrically. Wafers having an epitaxial layer produced using the susceptor have a high local flatness in the edge region.Type: ApplicationFiled: May 31, 2017Publication date: April 11, 2019Applicant: SILTRONIC AGInventor: Joerg HABERECHT
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Patent number: 8709156Abstract: Epitaxially coated silicon wafers are produced by placing a wafer polished on its front side on a susceptor in an epitaxy reactor, first pretreating under a hydrogen atmosphere and in a second and a third step with addition of an etching medium to the hydrogen atmosphere, and subsequently providing an epitaxial layer, wherein during the first and second steps the hydrogen flow rate is 20-100 slm, during the second and third steps the flow rate of the etching medium is 0.5-1.5 slm, during the second step the average temperature in the reactor chamber is 950-1050° C., and the power of heating elements above and below the susceptor is regulated such that there is a temperature difference of 5-30° C. between a radially symmetrical region encompassing the central axis of and a part lying outside this region; and during the third step the hydrogen flow rate is reduced to 0.5-10 slm. In a second method, during the third pretreatment step the flow rate of the etching medium is increased to 1.Type: GrantFiled: April 23, 2010Date of Patent: April 29, 2014Assignee: Siltronic AGInventor: Joerg Haberecht
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Patent number: 8372298Abstract: Epitaxially coated silicon wafers, are coated individually in an epitaxy reactor by a procedure in which a silicon wafer on a susceptor in the epitaxy reactor, is pretreated in a first step with a hydrogen flow rate of 1-100 slm and in a second step with hydrogen and an etching medium at a hydrogen flow rate of 1-100 slm, and an etching medium flow rate of 0.5-1.5 slm, at an average temperature of 950-1050° C., and is subsequently coated epitaxially, wherein, during the second pretreatment step, the power of heating elements is regulated such that there is a temperature difference of 5-30° C. between a radially symmetrical central region of the silicon wafer and an outer region of the silicon outside the central region.Type: GrantFiled: February 2, 2010Date of Patent: February 12, 2013Assignee: Siltronic AGInventor: Joerg Haberecht
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Patent number: 8268708Abstract: Silicon wafers polished on their front sides are individually placed on a susceptor in an epitaxy reactor and firstly pretreated under a hydrogen atmosphere, and secondly with addition of an etching medium with a flow rate of 1.5-5 slm to the hydrogen atmosphere, the hydrogen flow rate being 1-100 slm in both steps, and subsequently epitaxially coated on the polished front side, and then removed from the reactor. In a second method, gas flows introduced into the reactor by injectors are distributed into outer and inner zones of the chamber, such that the inner zone gas flow acts on a wafer central region and the outer zone gas flow acts on a wafer edge region, the inner/outer distribution of the etching medium I/O=0-0.75. Silicon wafers having an epitaxial layer having global flatness value GBIR of 0.02-0.06 ?m, relative to an edge exclusion of 2 mm are produced.Type: GrantFiled: January 5, 2010Date of Patent: September 18, 2012Assignee: Siltronic AGInventors: Joerg Haberecht, Christian Hager, Georg Brenninger
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Publication number: 20100294197Abstract: Epitaxially coated silicon wafers are produced by placing a wafer polished on its front side on a susceptor in an epitaxy reactor, first pretreating under a hydrogen atmosphere and in a second and a third step with addition of an etching medium to the hydrogen atmosphere, and subsequently providing an epitaxial layer, wherein during the first and second steps the hydrogen flow rate is 20-100 slm, during the second and third steps the flow rate of the etching medium is 0.5-1.5 slm, during the second step the average temperature in the reactor chamber is 950-1050° C., and the power of heating elements above and below the susceptor is regulated such that there is a temperature difference of 5-30° C. between a radially symmetrical region encompassing the central axis of and a part lying outside this region; and during the third step the hydrogen flow rate is reduced to 0.5-10 slm. In a second method, during the third pretreatment step the flow rate of the etching medium is increased to 1.Type: ApplicationFiled: April 23, 2010Publication date: November 25, 2010Applicant: Siltronic AGInventor: Joerg Haberecht
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Publication number: 20100213168Abstract: Epitaxially coated silicon wafers, are coated individually in an epitaxy reactor by a procedure in which a silicon wafer on a susceptor in the epitaxy reactor, is pretreated in a first step with a hydrogen flow rate of 1-100 slm and in a second step with hydrogen and an etching medium at a hydrogen flow rate of 1-100 slm, and an etching medium flow rate of 0.5-1.5 slm, at an average temperature of 950-1050° C., and is subsequently coated epitaxially, wherein, during the second pretreatment step, the power of heating elements is regulated such that there is a temperature difference of 5-30° C. between a radially symmetrical central region of the silicon wafer and an outer region of the silicon outside the central region.Type: ApplicationFiled: February 2, 2010Publication date: August 26, 2010Applicant: SILTRONIC AGInventor: Joerg Haberecht
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Publication number: 20100176491Abstract: Silicon wafers polished on their front sides are individually placed on a susceptor in an epitaxy reactor and firstly pretreated under a hydrogen atmosphere, and secondly with addition of an etching medium with a flow rate of 1.5-5 slm to the hydrogen atmosphere, the hydrogen flow rate being 1-100 slm in both steps, and subsequently epitaxially coated on the polished front side, and then removed from the reactor. In a second method, gas flows introduced into the reactor by injectors are distributed into outer and inner zones of the chamber, such that the inner zone gas flow acts on a wafer central region and the outer zone gas flow acts on a wafer edge region, the inner/outer distribution of the etching medium I/O=0-0.75. Silicon wafers having an epitaxial layer having global flatness value GBIR of 0.02-0.06 ?m, relative to an edge exclusion of 2 mm are produced.Type: ApplicationFiled: January 5, 2010Publication date: July 15, 2010Applicant: SILTRONIC AGInventors: Joerg Haberecht, Christian Hager, Georg Brenninger