Abstract: An architecture for content-aware compression and/or encryption of various segments of a application is disclosed. The architecture advantageously allows decompression and decryption units to be placed various levels of a memory hierarchy.

Abstract: An embedded systems architecture is disclosed which can flexibly handle compression of both instruction code and data.

Abstract: An embedded systems architecture is disclosed which can flexibly handle compression of both instruction code and data.

Abstract: A new compression and decompression architecture is herein disclosed which advantageously uses a plurality of parallel content addressable memories of different sizes to perform fast matching during compression.

Abstract: An architecture for content-aware compression and/or encryption of various segments of a application is disclosed. The architecture advantageously allows decompression and decryption units to be placed various levels of a memory hierarchy.

Abstract: A system architecture is disclosed that can support fast random access to encrypted memory.

Abstract: Code compression is known as an effective technique to reduce instruction memory size on an embedded system. However, code compression can also be very effective in increasing the processor-to-memory bandwidth and hence provide increased system performance. A code decompression engine having plurality of dictionary tables, coupled with decoding circuitry and appropriate control circuitry, is coupled between the processor core and the instruction cache. The code decompression engine provides one-cycle decompression of compressed instructions that are intermixed with uncompressed instructions, thereby increasing processor-to-memory bandwidth and avoiding processor stalls.

Abstract: A novel power minimizing hardware/software co-design approach is presented that partitions an embedded application into an application specific core and a software program that executes on a microprocessor core. As opposed to prior art approaches, the present approach is very comprehensive since it takes into consideration a whole embedded system. In addition, it partitions at the cost of a very small additional hardware effort. The experimental results show high energy savings while maintaining (or even slightly increasing) the performance of the initial design.

Abstract: Code compression is known as an effective technique to reduce instruction memory size on an embedded system. However, code compression can also be very effective in increasing the processor-to-memory bandwidth and hence provide increased system performance. A code decompression engine having plurality of dictionary tables, coupled with decoding circuitry and appropriate control circuitry, is coupled between the processor core and the instruction cache. The code decompression engine provides one-cycle decompression of compressed instructions that are intermixed with uncompressed instructions, thereby increasing processor-to-memory bandwidth and avoiding processor stalls.

Abstract: An instrument panel for a motor vehicle. The panel is adapted to cover the front passenger air bags with webs in one piece with a support preform of the instrument panel, in which case the webs are situated outside a passage contour of the front passenger air bag. The wall thickness of the support preform is reduced at least in sections in the area of the webs.

Abstract: An airbag device for motor vehicles has a housing in which an airbag expandable through a housing opening is located. The housing opening is covered by a flexible protective cover in the resting state of the airbag. The cover is provided with at least one tearing location. The cover flanks the airbag on all sides over at least a portion of its expansion path during expansion. The protective cover is provided with at least two tearing locations offset with respect to one another in the expansion direction such that the protective cover tears open in stages during the expansion of the airbag.