Patents by Inventor Joerg Keller

Joerg Keller has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240085800
    Abstract: A component for a projection exposure apparatus for semiconductor lithography, comprises an optical element and an actuator, which are force-fittingly connected to each other. The actuator at least locally deforms the optical element. The actuator can be configured to minimize the loss in rigidity at the peripheries delimiting the actuator on the imaging quality. A method for designing a component of projection exposure apparatus is provided.
    Type: Application
    Filed: November 13, 2023
    Publication date: March 14, 2024
    Inventors: Thilo Pollak, Dietmar Duerr, Irina Schrezenmeier, Joerg Tschischgale, Matthias Manger, Andreas Beljakov, Stefan Baueregger, Alexander Ostendorf, Dieter Bader, Markus Raab, Bastian Keller
  • Publication number: 20090194890
    Abstract: Embodiments of the invention relate generally to an integrated circuit and a memory module. In an embodiment of the invention, an integrated circuit is provided. The integrated circuit may include a semiconductor carrier including at least one electrically inactive region on an upper surface thereof, a passivation layer structure disposed above the upper surface of the semiconductor carrier, and at least one lithographic trench in the passivation layer structure above the at least one electrically inactive region on the upper surface of the semiconductor carrier.
    Type: Application
    Filed: January 31, 2008
    Publication date: August 6, 2009
    Inventors: Knut Kahlisch, Martin Reiss, Joerg Keller
  • Publication number: 20090189292
    Abstract: Embodiments of the invention relate to a semiconductor, a semiconductor module and to a method for manufacturing a semiconductor module. In an embodiment of the invention, an integrated circuit includes a plurality of connection pads on at least one side of the integrated circuit, which connection pads can be coupled electrically conductingly by means of a respective bond wire, wherein in at least an edge area on the side of the integrated circuit, on which the connection pads are arranged, a support frame portion is arranged which is configured such that bond wires adjacent to each other can be supported on the support frame portion at a distance from each other.
    Type: Application
    Filed: January 29, 2008
    Publication date: July 30, 2009
    Inventors: Martin Reiss, Knut Kahlisch, Joerg Keller
  • Patent number: 7279888
    Abstract: A handling unit includes a frame, at least one arrangement module, and at least one chip carrier. The frame has at least one recess for the interchangeable mounting of at least one of the arrangement modules. The arrangement module has at least one receptacle for the mounting of at least one chip carrier. The chip carrier has at least one chip seat for holding a chip.
    Type: Grant
    Filed: June 29, 2005
    Date of Patent: October 9, 2007
    Assignee: Infineon Technologies AG
    Inventors: Andreas Bischof, Michael Adam, Joerg Keller
  • Publication number: 20070001703
    Abstract: A handling unit includes a frame, at least one arrangement module, and at least one chip carrier. The frame has at least one recess for the interchangeable mounting of at least one of the arrangement modules. The arrangement module has at least one receptacle for the mounting of at least one chip carrier. The chip carrier has at least one chip seat for holding a chip.
    Type: Application
    Filed: June 29, 2005
    Publication date: January 4, 2007
    Inventors: Andreas Bischof, Michael Adam, Joerg Keller
  • Patent number: 5689636
    Abstract: Tracer systems should not influence running real-time systems such that the real-time demands thereof can no longer be met. In order to resolve this problem, the tracer system disclosed comprises a monitoring means that identifies the dynamic load on a real-time system caused by the tracer system and deactivates the tracer system when the dynamic load upwardly exceeds a specific threshold.
    Type: Grant
    Filed: September 28, 1994
    Date of Patent: November 18, 1997
    Assignee: Siemens Aktiengesellschaft
    Inventors: Ulrich Kleber, Hans-Joerg Keller