Patents by Inventor Joerg Kirchner
Joerg Kirchner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12341422Abstract: The techniques and circuits, described herein, include solutions for pass-through operation including overcurrent protection in buck-boost converters. In some aspects, first and second switches selectively couple inputs of a peak current comparator to inputs of an error amplifier during pass-through operation. As part of peak current control scheme, one of the peak current comparator inputs is coupled to a current sensor that senses a current through an inductor of the buck-boost converter. As a result, an output of the error amplifier tracks the inductor current during pass-through mode, which may be utilized to implement inductor overcurrent protection in the pass-through mode.Type: GrantFiled: April 28, 2023Date of Patent: June 24, 2025Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Florian Neveu, Stefan Schimonsky, Joerg Kirchner
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Publication number: 20250155958Abstract: An example apparatus includes: switching converter circuitry having an input terminal and an output terminal; and peak current control circuitry coupled to the switching converter circuitry, the peak current control circuitry including: error amplifier having an input terminal and an output terminal; power saving mode (PSM) entry circuitry having a first input terminal, a second input terminal, and an output terminal, the first input terminal of the PSM entry circuitry coupled to the input terminal of the switching converter circuitry, the second input terminal of the PSM entry circuitry coupled to the output terminal of the switching converter circuitry and the input terminal of the error amplifier; and comparison circuitry having a first input terminal and a second input terminal, the first input terminal of the comparison circuitry coupled to the output terminal of the error amplifier.Type: ApplicationFiled: January 31, 2024Publication date: May 15, 2025Inventors: Joerg Kirchner, Florian Neveu, Stefan Schimonsky
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Publication number: 20240364210Abstract: The techniques and circuits, described herein, include solutions for pass-through operation including overcurrent protection in buck-boost converters. In some aspects, first and second switches selectively couple inputs of a peak current comparator to inputs of an error amplifier during pass-through operation. As part of peak current control scheme, one of the peak current comparator inputs is coupled to a current sensor that senses a current through an inductor of the buck-boost converter. As a result, an output of the error amplifier tracks the inductor current during pass-through mode, which may be utilized to implement inductor overcurrent protection in the pass-through mode.Type: ApplicationFiled: April 28, 2023Publication date: October 31, 2024Inventors: Florian Neveu, Stefan Schimonsky, Joerg Kirchner
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Patent number: 11569736Abstract: A soft-start circuit includes an error amplifier, a reference voltage ramp circuit, and a minimum current clamp circuit. The error amplifier is configured to generate a difference voltage representing a difference of a feedback voltage and a reference voltage ramp. The reference voltage ramp circuit is configured to generate the reference voltage ramp. The minimum current clamp circuit is configured to clamp an output of the error amplifier to a predetermined minimum voltage.Type: GrantFiled: February 25, 2021Date of Patent: January 31, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Joerg Kirchner, Stefan Schimonsky
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Patent number: 11552566Abstract: To facilitate current sensing for valley current-controlled power converters, an example apparatus includes a comparator having a first terminal, a second terminal, and an output. A first transistor has a first drain coupled to the first terminal of the comparator. A second transistor has a second drain coupled to the first terminal of the comparator. A third transistor has a third drain coupled to the second terminal of the comparator.Type: GrantFiled: February 15, 2021Date of Patent: January 10, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Joerg Kirchner, Stefan Dietrich, Ivan Shumkov, Christian Harder
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Publication number: 20220271649Abstract: A soft-start circuit includes an error amplifier, a reference voltage ramp circuit, and a minimum current clamp circuit. The error amplifier is configured to generate a difference voltage representing a difference of a feedback voltage and a reference voltage ramp. The reference voltage ramp circuit is configured to generate the reference voltage ramp. The minimum current clamp circuit is configured to clamp an output of the error amplifier to a predetermined minimum voltage.Type: ApplicationFiled: February 25, 2021Publication date: August 25, 2022Inventors: Joerg KIRCHNER, Stefan SCHIMONSKY
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Patent number: 11303210Abstract: Aspects of the present disclosure provide for a circuit. In at least some examples, the circuit includes a first switch coupled between a first node and a second node and a second switch coupled between a third node and the second node. The circuit further includes a resistor coupled between the second node and a fourth node and a capacitor comprising a first terminal coupled to the fourth node and a second terminal. The circuit further includes a transistor comprising a drain terminal coupled to the third node, a source terminal coupled to a fifth node, and a gate terminal and an amplifier comprising a first input terminal coupled to the fifth node, a second input terminal coupled to the fourth node, and an output terminal coupled to a sixth node.Type: GrantFiled: December 9, 2019Date of Patent: April 12, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Ivan Shumkov, Christian Harder, Erich-Johann Bayer, Joerg Kirchner, Gaetano Petrina
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Patent number: 11258363Abstract: Aspects of the disclosure provide for a circuit comprising a power converter controller. In an example, the power converter controller is configured to receive a signal representative of a current of a power converter, compare the signal representative of the current of the power converter to an error signal and generate a peak current detection signal having an asserted value when the signal representative of the current of the power converter is not less than the error signal. A state machine circuit is coupled the peak current detection circuit. The state machine circuit is configured to receive the peak current detection signal, a clock signal, and a timer signal and implement a state machine to generate at least one control signal for controlling a mode and a phase of operation of the power converter based on values of the peak current detection signal, the clock signal, and the timer signal.Type: GrantFiled: December 12, 2019Date of Patent: February 22, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Joerg Kirchner, Stefan Dietrich, Gaetano Maria Walter Petrina
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Publication number: 20210184575Abstract: Aspects of the disclosure provide for a circuit comprising a power converter controller. In an example, the power converter controller is configured to receive a signal representative of a current of a power converter, compare the signal representative of the current of the power converter to an error signal and generate a peak current detection signal having an asserted value when the signal representative of the current of the power converter is not less than the error signal. A state machine circuit is coupled the peak current detection circuit. The state machine circuit is configured to receive the peak current detection signal, a clock signal, and a timer signal and implement a state machine to generate at least one control signal for controlling a mode and a phase of operation of the power converter based on values of the peak current detection signal, the clock signal, and the timer signal.Type: ApplicationFiled: December 12, 2019Publication date: June 17, 2021Inventors: Joerg KIRCHNER, Stefan DIETRICH, Gaetano Maria Walter PETRINA
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Publication number: 20210175804Abstract: Aspects of the present disclosure provide for a circuit. In at least some examples, the circuit includes a first switch coupled between a first node and a second node and a second switch coupled between a third node and the second node. The circuit further includes a resistor coupled between the second node and a fourth node and a capacitor comprising a first terminal coupled to the fourth node and a second terminal. The circuit further includes a transistor comprising a drain terminal coupled to the third node, a source terminal coupled to a fifth node, and a gate terminal and an amplifier comprising a first input terminal coupled to the fifth node, a second input terminal coupled to the fourth node, and an output terminal coupled to a sixth node.Type: ApplicationFiled: December 9, 2019Publication date: June 10, 2021Inventors: Ivan SHUMKOV, Christian HARDER, Erich-Johann BAYER, Joerg KIRCHNER, Gaetano PETRINA
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Publication number: 20210167687Abstract: To facilitate current sensing for valley current-controlled power converters, an example apparatus includes a comparator having a first terminal, a second terminal, and an output. A first transistor has a first drain coupled to the first terminal of the comparator. A second transistor has a second drain coupled to the first terminal of the comparator. A third transistor has a third drain coupled to the second terminal of the comparator.Type: ApplicationFiled: February 15, 2021Publication date: June 3, 2021Inventors: Joerg Kirchner, Stefan Dietrich, Ivan Shumkov, Christian Harder
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Patent number: 10924015Abstract: Methods, systems, and apparatus to facilitate current sensing for valley current-controlled power converters are disclosed. An example apparatus includes a comparator including a first terminal, a second terminal, and an output. The apparatus further includes a first transistor including a first drain coupled to the first terminal of the comparator. The apparatus further includes a second transistor including a second drain coupled to the first terminal of the comparator. The apparatus further includes a third transistor including a third drain coupled to the second terminal of the comparator.Type: GrantFiled: May 25, 2018Date of Patent: February 16, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Joerg Kirchner, Stefan Dietrich, Ivan Shumkov, Christian Harder
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Patent number: 10871810Abstract: A power supply system can include at least one power switch to generate an output current based on an input voltage in response to a switching signal to generate an output voltage. A feedback system generates a feedback current based on the output voltage. A mode detector generates a control current associated with the output current based on the feedback current and selects between a pulse-width modulation (PWM) mode and a pulse mode based on an amplitude of the control current. The PWM mode is associated with a sequential on-time and off-time of the at least one power switch, and the pulse mode is associated with adding an idle time between the on-time and the off-time of the at least one power switch based on the switching signal. A gate driver system generates the switching signal based on the mode.Type: GrantFiled: August 21, 2018Date of Patent: December 22, 2020Assignee: Texas Instruments IncorporatedInventors: Joerg Kirchner, Stefan Dietrich, Julian Becker, Eduardas Jodka
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Publication number: 20200358357Abstract: A DC/DC switching converter includes high-side and low-side power NFETs coupled in series between a first pin for coupling to a first supply voltage and a second pin for coupling to a second supply voltage. A switch-node is coupled to a third pin. A first gate driver is coupled to drive a gate voltage on the high-side power NFET at a first rate and a second gate driver is coupled to drive the gate voltage of the high-side power NFET at a second rate that is higher than the first rate. A comparator is coupled to the first pin and to the gate of the high-side power NFET and further coupled to turn on the second gate driver when a gate voltage of the high-side power NFET is equal to the first supply voltage coupled to the first pin plus a threshold voltage of the high-side power NFET.Type: ApplicationFiled: May 6, 2019Publication date: November 12, 2020Inventors: Gaetano Maria Walter Petrina, Joerg Kirchner
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Patent number: 10819237Abstract: A DC/DC switching converter includes high-side and low-side power NFETs coupled in series between a first pin for coupling to a first supply voltage and a second pin for coupling to a second supply voltage. A switch-node is coupled to a third pin. A first gate driver is coupled to drive a gate voltage on the high-side power NFET at a first rate and a second gate driver is coupled to drive the gate voltage of the high-side power NFET at a second rate that is higher than the first rate. A comparator is coupled to the first pin and to the gate of the high-side power NFET and further coupled to turn on the second gate driver when a gate voltage of the high-side power NFET is equal to the first supply voltage coupled to the first pin plus a threshold voltage of the high-side power NFET.Type: GrantFiled: May 6, 2019Date of Patent: October 27, 2020Assignee: Texas Instruments IncorporatedInventors: Gaetano Maria Walter Petrina, Joerg Kirchner
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Patent number: 10763748Abstract: Disclosed examples include inverting buck-boost DC-DC converter circuits with a switching circuit to alternate between first and second buck mode phases for buck operation in a first mode, including connecting an inductor and a capacitor in series between an input node and a reference node to charge the inductor and the capacitor in the first buck mode phase, and connecting the inductor and the capacitor in parallel between an output node and the reference node to discharge the inductor and the capacitor to the output node.Type: GrantFiled: June 1, 2018Date of Patent: September 1, 2020Assignee: Texas Instruments IncorporatedInventors: Ivan Shumkov, Erich Bayer, Joerg Kirchner, Ruediger Ganz, Michael Lueders, Martin Priess, Nicola Rasera
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Patent number: 10651742Abstract: A current measurement linearization circuit for a DC/DC boost converter includes a back-gate sensing transistor and a back-gate reset transistor. The back-gate sensing transistor has a first terminal coupled to a first body contact of a high-side power transistor and a second terminal coupled to a second body contact of a first replica transistor in a valley-current sensing circuit. The back-gate reset transistor has a first terminal coupled to a max reference voltage that is equal to the greater of an input voltage and an output voltage and a second terminal coupled to the second body contact.Type: GrantFiled: March 5, 2019Date of Patent: May 12, 2020Assignee: Texas Instruments IncorporatedInventors: Stefan Dietrich, Joerg Kirchner
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Publication number: 20200076308Abstract: A current measurement linearization circuit for a DC/DC boost converter includes a back-gate sensing transistor and a back-gate reset transistor. The back-gate sensing transistor has a first terminal coupled to a first body contact of a high-side power transistor and a second terminal coupled to a second body contact of a first replica transistor in a valley-current sensing circuit. The back-gate reset transistor has a first terminal coupled to a max reference voltage that is equal to the greater of an input voltage and an output voltage and a second terminal coupled to the second body contact.Type: ApplicationFiled: March 5, 2019Publication date: March 5, 2020Inventors: Stefan Dietrich, Joerg Kirchner
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Publication number: 20200064893Abstract: A power supply system can include at least one power switch to generate an output current based on an input voltage in response to a switching signal to generate an output voltage. A feedback system generates a feedback current based on the output voltage. A mode detector generates a control current associated with the output current based on the feedback current and selects between a pulse-width modulation (PWM) mode and a pulse mode based on an amplitude of the control current. The PWM mode is associated with a sequential on-time and off-time of the at least one power switch, and the pulse mode is associated with adding an idle time between the on-time and the off-time of the at least one power switch based on the switching signal. A gate driver system generates the switching signal based on the mode.Type: ApplicationFiled: August 21, 2018Publication date: February 27, 2020Inventors: JOERG KIRCHNER, STEFAN DIETRICH, JULIAN BECKER, EDUARDAS JODKA
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Patent number: 10523116Abstract: A timer for creating a stable on time. The timer may have a reference voltage source, and an input voltage source. The voltage sources providing voltage that can be applied to a various circuit components such as capacitors, inductors, resistors, diodes, transistors, or other components. The reference voltage source may also be modified by a set of transistors coupled as a diode before being seen by an input of a timer comparator. The reference and input voltage source signals, which may be modified by circuit components, are compared by the timer comparator and then output as a timer control signal. The timer control signal may control a voltage converter, or the switches of a voltage converter.Type: GrantFiled: September 10, 2018Date of Patent: December 31, 2019Assignee: Texas Instruments IncorporatedInventors: Stefan Dietrich, Joerg Kirchner, Ruediger Ganz