Patents by Inventor Joerg Mensinger

Joerg Mensinger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • System transmitting data in equidistance cycles using successive synchronization signals for detecting and signaling access violations
    Patent number: 6813664
    Abstract: A user terminal (1) having a communications processor (10) that carries out a cyclic data transmission. During a cyclic part (ZYK,x) of a cycle (Z,x) in which user data are transmitted, a DP application may not access the memory (14, 15). In the communications processor (10), the memory (14, 15) stores a process image. The communications processor (10), for the purpose of synchronization, transmits at the beginning of a cycle a cycle start interrupt (ZSI,x) and at the end of the cyclic part (ZYK,x) a cycle end interrupt (ZEI,x). Once the arithmetic unit (5, 7, 8) has accessed the memory it releases the interrupts. The duration (&Dgr;T′s2,1; &Dgr;T′e2,1) between two successive interrupts serves to detect access violations and to initiate appropriate fault treatment measures.
    Type: Grant
    Filed: January 31, 2003
    Date of Patent: November 2, 2004
    Assignee: Siemens Aktiengesellschaft
    Inventors: Christoph Koellner, Otmar Katzenberger, Joerg Mensinger, Heinrich Rudi
  • Network that transmits data in equidistant cycles
    Publication number: 20030200327
    Abstract: A user terminal (1) having a communications processor (10) that carries out a cyclic data transmission. During a cyclic part (ZYK,x) of a cycle (Z,x) in which user data are transmitted, a DP application may not access the memory (14, 15). In the communications processor (10), the memory (14, 15) stores a process image. The communications processor (10), for the purpose of synchronization, transmits at the beginning of a cycle a cycle start interrupt (ZSI,x) and at the end of the cyclic part (ZYK,x) a cycle end interrupt (ZEI,x). Once the arithmetic unit (5, 7, 8) has accessed the memory it releases the interrupts. The duration (&Dgr;T′s2,1; &Dgr;T′e2,1) between two successive interrupts serves to detect access violations and to initiate appropriate fault treatment measures.
    Type: Application
    Filed: January 31, 2003
    Publication date: October 23, 2003
    Applicant: SIEMENS AG
    Inventors: Christoph Koellner, Otmar Katzenberger, Joerg Mensinger, Heinrich Rudi