Patents by Inventor Joerg Moser

Joerg Moser has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130061842
    Abstract: Wire spools used for multiple wire saws for slicing one or more wafers from a workpiece composed of semiconductor material using a wire web including parallel wire sections coated with bonded abrasive grain. The wire spools include a first wire spool configured as a dispensing spool and a second wire spool configured as a receiver spool. A sawing wire coated with bonded abrasive grain runs from the first wire spool via at least one deflection roll to the wire web and from the wire web via at least one deflection roll to the second wire spool. The sawing wire enters into guide grooves of the deflection rolls at an alignment angle ?1 and exits the guide grooves of the deflection rolls at an alignment angle ?2. The sawing wire has a single layer winding on each of the first and second wire spools.
    Type: Application
    Filed: August 27, 2012
    Publication date: March 14, 2013
    Applicant: SILTRONIC AG
    Inventors: Joachim Junge, Joerg Moser
  • Patent number: 7767470
    Abstract: A semiconductor wafer has a front side, a rear side and an edge which runs along the circumference of the semiconductor wafer and which connects the front side and the rear side of the edge having a defined edge profile, the edge profile being substantially constant over the entire circumference of the semiconductor wafer. A method for producing such a wafer allows for production of a multiplicity of semiconductor wafers, the edge profile being substantially constant from semiconductor wafer to semiconductor wafer.
    Type: Grant
    Filed: July 26, 2007
    Date of Patent: August 3, 2010
    Assignee: Siltronic AG
    Inventors: Peter Wagner, Hans Adolf Gerber, Anton Huber, Joerg Moser
  • Patent number: 7704126
    Abstract: Semiconductor wafers with profiled edges, are produced with decreased losses due to edge or other damage by separating a semiconductor wafer from a crystal; profiling the edge in a profile producing step wherein the edge is mechanically machined to a profile that is true to scale with respect to a predefined target profile; mechanically machining the wafer to reduce the a thickness of the semiconductor wafer; and machining the edge profile to acquire the target profile.
    Type: Grant
    Filed: May 4, 2007
    Date of Patent: April 27, 2010
    Assignee: Siltronic AG
    Inventors: Joachim Mattes, Anton Huber, Joerg Moser
  • Publication number: 20080036040
    Abstract: A semiconductor wafer has a front side, a rear side and an edge which runs along the circumference of the semiconductor wafer and which connects the front side and the rear side of the edge having a defined edge profile, the edge profile being substantially constant over the entire circumference of the semiconductor wafer. A method for producing such a wafer allows for production of a multiplicity of semiconductor wafers, the edge profile being substantially constant from semiconductor wafer to semiconductor wafer.
    Type: Application
    Filed: July 26, 2007
    Publication date: February 14, 2008
    Applicant: SILTRONIC AG
    Inventors: Peter Wagner, Hans Adolf Gerber, Anton Huber, Joerg Moser