Patents by Inventor Joerg Radecker
Joerg Radecker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8722479Abstract: Generally, the present disclosure is directed to a method of at least reducing unwanted erosion of isolation structures of a semiconductor device during fabrication. One illustrative method disclosed includes forming an isolation structure in a semiconducting substrate and forming a conductive protection ring above plurality isolation structure.Type: GrantFiled: May 25, 2011Date of Patent: May 13, 2014Assignee: GLOBALFOUNDRIES Inc.Inventors: Hans-Juergen Thees, Stephan Kronholz, Joerg Radecker
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Patent number: 8716102Abstract: A method includes forming a patterned mask comprised of a polish stop layer positioned above a protection layer above a substrate, performing at least one etching process through the patterned mask layer on the substrate to define a trench in the substrate, and forming a layer of silicon dioxide above the patterned mask layer such that the layer of silicon dioxide overfills the trench. The method also includes removing portions of the layer of silicon dioxide positioned outside of the trench to define an isolation structure, performing a dry, selective chemical oxide etching process that removes silicon dioxide selectively relative to the material of the polish stop layer to reduce an overall height of the isolation structure, and performing a selective wet etching process to remove the polish stop layer selectively relative to the isolation region.Type: GrantFiled: August 14, 2012Date of Patent: May 6, 2014Assignee: GLOBALFOUNDRIES Inc.Inventors: Frank Jakubowski, Joerg Radecker, Joanna Wasyluk
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Patent number: 8679940Abstract: Methods for fabricating semiconductor devices are provided. In an embodiment, a method for fabricating a semiconductor device includes forming a planarization stop layer overlying a semiconductor substrate. A trench is etched through the planarization stop layer and into the semiconductor substrate and is filled with an isolation material. The isolation material is planarized to establish a top surface of the isolation material coplanar with the planarization stop layer. In the method, a dry deglaze process is performed to remove a portion of the planarization stop layer and a portion of the isolation material to lower the top surface of the isolation material to a desired stepheight above the semiconductor substrate.Type: GrantFiled: February 17, 2012Date of Patent: March 25, 2014Assignee: GLOBALFOUNDRIES, Inc.Inventors: Frank Jakubowski, Jörg Radecker, Frank Ludwig
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Publication number: 20140051227Abstract: A method includes forming a patterned mask comprised of a polish stop layer positioned above a protection layer above a substrate, performing at least one etching process through the patterned mask layer on the substrate to define a trench in the substrate, and forming a layer of silicon dioxide above the patterned mask layer such that the layer of silicon dioxide overfills the trench. The method also includes removing portions of the layer of silicon dioxide positioned outside of the trench to define an isolation structure, performing a dry, selective chemical oxide etching process that removes silicon dioxide selectively relative to the material of the polish stop layer to reduce an overall height of the isolation structure, and performing a selective wet etching process to remove the polish stop layer selectively relative to the isolation region.Type: ApplicationFiled: August 14, 2012Publication date: February 20, 2014Applicant: GLOBALFOUNDRIES INC.Inventors: Frank Jakubowski, Joerg Radecker, Joanna Wasyluk
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Patent number: 8603895Abstract: In one example, the method includes forming a patterned etch mask above a semiconducting substrate, performing an etching process through the patterned etch mask to thereby form a trench in the substrate, performing a first deposition process to form a first layer of insulating material above the patterned etch mask and in the trench, and performing an etching process on the first layer of insulating material such that the post-etch thickness of the first layer of insulating material is less than an as-deposited thickness of the first layer of insulating material. The method also includes performing a second deposition process to form a second layer of insulating material on the etched first layer of insulating material, wherein the second layer of insulating material overfills the trench, and removing portions of the etched first layer of insulating material and the second layer of insulating material positioned above the patterned etch mask.Type: GrantFiled: September 11, 2012Date of Patent: December 10, 2013Assignee: GLOBALFOUNDRIES Inc.Inventors: Frank Jakubowski, Joerg Radecker, Ralf Willecke
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Patent number: 8569143Abstract: Methods and provided for fabricating a semiconductor IC having a hardened shallow trench isolation (STI). In accordance with one embodiment the method includes providing a semiconductor substrate and forming an etch mask having an opening exposing a portion the semiconductor substrate. The exposed portion is etched to form a trench extending into the semiconductor substrate and an oxide is deposited to at least partially fill the trench. At least the surface portion of the oxide is plasma nitrided to form a nitrided oxide layer and then the etch mask is removed.Type: GrantFiled: June 23, 2011Date of Patent: October 29, 2013Assignee: GLOBALFOUNDRIES, Inc.Inventors: Thorsten Kammler, Joerg Radecker, Christof Streck
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Publication number: 20130217205Abstract: Methods for fabricating semiconductor devices are provided. In an embodiment, a method for fabricating a semiconductor device includes forming a planarization stop layer overlying a semiconductor substrate. A trench is etched through the planarization stop layer and into the semiconductor substrate and is filled with an isolation material. The isolation material is planarized to establish a top surface of the isolation material coplanar with the planarization stop layer. In the method, a dry deglaze process is performed to remove a portion of the planarization stop layer and a portion of the isolation material to lower the top surface of the isolation material to a desired stepheight above the semiconductor substrate.Type: ApplicationFiled: February 17, 2012Publication date: August 22, 2013Applicant: GLOBALFOUNDRIES Inc.Inventors: Frank Jakubowski, Jörg Radecker, Frank Ludwig
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Publication number: 20120329239Abstract: Methods and provided for fabricating a semiconductor IC having a hardened shallow trench isolation (STI). In accordance with one embodiment the method includes providing a semiconductor substrate and forming an etch mask having an opening exposing a portion the semiconductor substrate. The exposed portion is etched to form a trench extending into the semiconductor substrate and an oxide is deposited to at least partially fill the trench. At least the surface portion of the oxide is plasma nitrided to form a nitrided oxide layer and then the etch mask is removed.Type: ApplicationFiled: June 23, 2011Publication date: December 27, 2012Applicant: GLOBALFOUNDRIES Inc.Inventors: Thorsten Kammler, Joerg Radecker, Christof Streck
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Publication number: 20120302037Abstract: Generally, the present disclosure is directed to a method of at least reducing unwanted erosion of isolation structures of a semiconductor device during fabrication. One illustrative method disclosed includes forming an isolation structure in a semiconducting substrate and forming a conductive protection ring above plurality isolation structure.Type: ApplicationFiled: May 25, 2011Publication date: November 29, 2012Applicant: GLOBALFOUNDRIES INC.Inventors: Hans-Juergen Thees, Stephan Kronholz, Joerg Radecker
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Publication number: 20090321805Abstract: One embodiment relates to an integrated circuit that includes a conductive line that is arranged in a groove in a semiconductor body. An insulating material is disposed over the conductive line. This insulating material includes a first insulating layer comprising a horizontal portion, and a second insulating layer that is disposed over the first insulating layer. Other methods, devices, and systems are also disclosed.Type: ApplicationFiled: June 30, 2008Publication date: December 31, 2009Applicant: Qimonda AGInventors: Johannes von Kluge, Arnd Scholz, Joerg Radecker, Matthias Patz, Stephan Kudelka, Alejandro Avellan
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Publication number: 20080315326Abstract: An integrated circuit having an active semiconductor device is formed comprising a trench defined by conductor lines previously formed.Type: ApplicationFiled: June 21, 2007Publication date: December 25, 2008Inventors: Werner Graf, Ines Uhlig, Daniel Koehler, Joerg Radecker, Lars Heineck
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Publication number: 20080230839Abstract: The invention is related to a method of producing a semiconductor structure comprising the steps of: fabricating a gate stack structure and oxidizing at least a portion of the gate stack structure's sidewalls, wherein the step of oxidizing is carried out at a temperature below 500° C. using a process gas which comprises oxygen radicals.Type: ApplicationFiled: March 23, 2007Publication date: September 25, 2008Inventors: Joern Regul, Joerg Radecker, Olaf Storbeck, Kristin Schupke, Tobias Mono
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Patent number: 7125778Abstract: A description is given of a method for a selective masking of a structure with a small structure surface with respect to a structure with a larger structure surface. To that end, the structures are filled with a covering layer. The covering layer is formed with a larger thickness above the first structure, which has the larger structure surface, than above the second structure. Afterward, the covering layer is removed by a homogeneous removal method, so that first the structure surface of the second structure is uncovered. A simple self-aligning method for fabricating a mask for uncovering the second structure is thus provided.Type: GrantFiled: August 27, 2002Date of Patent: October 24, 2006Assignee: Infineon Technologies AGInventors: Dirk Efferenn, Ulrike Grüning Von Schwerin, Hans-Peter Moll, Jörg Radecker, Andreas Wich-Glasen
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Patent number: 7052970Abstract: In order to produce insulator structures (8), insulator trenches (21) with aspect ratios of greater than 4:1 are introduced into a semiconductor substrate (1) from a substrate surface (10) and filled with an insulator filling (3). The insulator filling (3) is formed from a plurality of portions (31, 32, 33, 34) which are deposited successively in situ in an HDP/CVD process chamber in the course of an HDP/CVD deposition process. A main layer (33) is provided made from fluorine-doped silicon oxide with good filling properties. A barrier layer (32) is formed directly before the deposition of the main layer (33), said barrier layer preventing an outgassing of the fluorine from the fluorine-doped silicon oxide (33), an interaction of the fluorine with the semiconductor substrate (1) and a formation of defect areas (6) with oxide of low quality in the area of the insulator filling (3). The barrier (32) makes it possible to form nondegrading p-channel transistors (73) in the area of the substrate surface (10).Type: GrantFiled: March 12, 2004Date of Patent: May 30, 2006Assignee: Infineon Technologies AGInventor: Joerg Radecker
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Patent number: 6908831Abstract: A method for encapsulating a filling in a trench of a semiconductor substrate includes providing a first barrier layer in a trench and a second barrier layer disposed above the first barrier layer. The trench is filled with a filling, which is subsequently etched back in an upper trench section, so that a hole is produced and a filling residue remains in a lower trench section. Subsequently, a non-conformal cover layer is provided in an upper trench section, so that the cover layer of a bottom region has a first thickness greater than a second thickness of a wall region of the cover layer. The cover layer and the second barrier layer are isotropically etched-back and removed from the upper trench section, and the first barrier layer remains. The bottom region remains covered resulting in the filling residue being encapsulated by the first barrier layer and the residual cover layer.Type: GrantFiled: October 15, 2004Date of Patent: June 21, 2005Assignee: Infineon Technologies AGInventors: Lincoln O'Riain, Jörg Radecker
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Publication number: 20040241929Abstract: In order to produce insulator structures (8), insulator trenches (21) with aspect ratios of greater than 4:1 are introduced into a semiconductor substrate (1) from a substrate surface (10) and filled with an insulator filling (3). The insulator filling (3) is formed from a plurality of portions (31, 32, 33, 34) which are deposited successively in situ in an HDP/CVD process chamber in the course of an HDP/CVD deposition process. A main layer (33) is provided made from fluorine-doped silicon oxide with good filling properties. A barrier layer (32) is formed directly before the deposition of the main layer (33), said barrier layer preventing an outgassing of the fluorine from the fluorine-doped silicon oxide (33), an interaction of the fluorine with the semiconductor substrate (1) and a formation of defect areas (6) with oxide of low quality in the area of the insulator filling (3). The barrier (32) makes it possible to form nondegrading p-channel transistors (73) in the area of the substrate surface (10).Type: ApplicationFiled: March 12, 2004Publication date: December 2, 2004Inventor: Joerg Radecker