Abstract: A delay locked loop based clocking circuit includes a lead delay line followed by a period delay line. The lead delay line receives an input clock signal and includes an analog delay control input. The period delay line has a plurality of taps and an analog delay control input, and is operated such that the N taps divide a single period of an input clock. A selected tap of the period delay line, sometimes called a “virtual zero-degree tap,” is fed back and phase-compared with the input clock signal to adjust the delay of the lead delay line.