Patents by Inventor Joerg Stender

Joerg Stender has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor memory having a redundancy circuit for word lines and method for operating the memory
    Patent number: 6570793
    Abstract: A redundancy circuit for a semiconductor memory having word lines and redundant word lines is described. The redundancy circuit activates the word line at the same time as checking to determine whether the applied address per word line is the address of a defective word line, and deactivates the word line again if it is determined that the applied address is the address of a defective word line.
    Type: Grant
    Filed: August 8, 2001
    Date of Patent: May 27, 2003
    Assignee: Infineon Technologies AG
    Inventor: Jörg Stender
  • Delay locked loop
    Publication number: 20020041196
    Abstract: A delay locked loop based clocking circuit includes a lead delay line followed by a period delay line. The lead delay line receives an input clock signal and includes an analog delay control input. The period delay line has a plurality of taps and an analog delay control input, and is operated such that the N taps divide a single period of an input clock. A selected tap of the period delay line, sometimes called a “virtual zero-degree tap,” is fed back and phase-compared with the input clock signal to adjust the delay of the lead delay line.
    Type: Application
    Filed: July 17, 2001
    Publication date: April 11, 2002
    Inventors: Paul Demone, Joerg Stender, Jamal Benzreba, Bruce Millar, Xiao Luo