Patents by Inventor Joerg Walter
Joerg Walter has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11163579Abstract: Generating instructions, in particular for mailbox verification in a simulation environment. A sequence of instructions is received, as well as selection data representative of a plurality of commands including a special command. Repeatedly selecting one of the plurality of commands and outputting an instruction based on the selected command. The outputting of an instruction includes outputting a next instruction in the sequence of instructions if the selected command is the special command, and outputting an instruction associated with the command if the selected command is not the special command.Type: GrantFiled: November 6, 2018Date of Patent: November 2, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Joerg Deutschle, Ursel Hahn, Joerg Walter, Ernst-Dieter Weissenberger
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Patent number: 10936517Abstract: A data processing apparatus includes a number of processor cores, a shared processor cache, a bus unit and a bus controller. The shared processor cache is connected to each of the processor cores and to a main memory. The bus unit is connected to the shared processor cache by a bus controller for transferring data to/from an I/O device. In order to achieve further improvements to the data transfer rate between the processor cache and I/O devices, the bus controller is configured, in response to receiving a descriptor from a processor core, to perform a direct memory access to the shared processor cache for transferring data according to the descriptor from the shared processor cache to the I/O device via the bus unit.Type: GrantFiled: June 25, 2019Date of Patent: March 2, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Norbert Hagspiel, Sascha Junghans, Matthias Klein, Joerg Walter
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Patent number: 10830818Abstract: It is determined, if a simulated hardware signal of a design for an electronic circuit has an influence on a checker for simulation errors. To achieve this, a checker control flow database is generated for a static code description containing checkers and concerned simulated signals. Further, a database based on the output of instrumented verification code is generated, thus gaining dynamic information about the verification code. Herein, the hardware signal values will be associated with colored values or, alternatively, attributed values. For the checkers in the checker control flow database, a list of attributes is generated and stored. Based on the above operations, a hardware signal database is generated, wherein hardware signals are mapped to a list of checkers, based on determining, for each checker in the checker database, the associated hardware signals from its list of attributed values.Type: GrantFiled: September 25, 2017Date of Patent: November 10, 2020Assignee: International Business Machines CorporationInventors: Carsten Greiner, Minh Cuong Tran, Gerrit Koch, Joerg Walter
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Patent number: 10823782Abstract: It is determined, if a simulated hardware signal of a design for an electronic circuit has an influence on a checker for simulation errors. To achieve this, a checker control flow database is generated for a static code description containing checkers and concerned simulated signals. Further, a database based on the output of instrumented verification code is generated, thus gaining dynamic information about the verification code. Herein, the hardware signal values will be associated with colored values or, alternatively, attributed values. For the checkers in the checker control flow database, a list of attributes is generated and stored. Based on the above operations, a hardware signal database is generated, wherein hardware signals are mapped to a list of checkers, based on determining, for each checker in the checker database, the associated hardware signals from its list of attributed values.Type: GrantFiled: November 8, 2017Date of Patent: November 3, 2020Assignee: International Business Machines CorporationInventors: Carsten Greiner, Minh Cuong Tran, Gerrit Koch, Joerg Walter
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Patent number: 10747625Abstract: Automatically configuring backup client systems and backup server systems in a backup environment includes the following steps: determining if a new backup client system is available in the backup environment; in case of an available new backup client system a backup configuration module performs the sub-steps of: determining data types the new backup client system has to backup; determining corresponding backup policies for the determined data types based on a backup policy table mapping data types with backup policies; selecting a backup server system for the determined data types based on a backup server table including connection details of available backup server systems; configuring the determined backup policies for the data types of the new backup client system on the selected backup server systems; and updating the backup server table with an identifier of the new backup client system and an identifier of the backup policy.Type: GrantFiled: December 27, 2017Date of Patent: August 18, 2020Assignee: International Business Machines CorporationInventors: Andre Gaschler, Nils Haustein, Dominic Mueller-Wicke, Tim U. Scheideler, Joerg Walter
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Publication number: 20200224609Abstract: A device for injecting water into an internal combustion having a tank for storage and provision of water, an injector for injecting the water into the internal combustion engine, which injector is connected to the tank, a control unit for controlling the injector 6, and a decontamination unit which has at least one element with a contact surface which, with formation of a surface contact with the water, acts in a decontaminating manner to provide decontaminated water for injection.Type: ApplicationFiled: June 27, 2018Publication date: July 16, 2020Inventors: Jan Hodgson, Ewald Renner, Marc Völker, Joerg Walter
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Publication number: 20190332559Abstract: A data processing apparatus includes a number of processor cores, a shared processor cache, a bus unit and a bus controller. The shared processor cache is connected to each of the processor cores and to a main memory. The bus unit is connected to the shared processor cache by a bus controller for transferring data to/from an I/O device. In order to achieve further improvements to the data transfer rate between the processor cache and I/O devices, the bus controller is configured, in response to receiving a descriptor from a processor core, to perform a direct memory access to the shared processor cache for transferring data according to the descriptor from the shared processor cache to the I/O device via the bus unit.Type: ApplicationFiled: June 25, 2019Publication date: October 31, 2019Inventors: Norbert HAGSPIEL, Sascha JUNGHANS, Matthias KLEIN, Joerg WALTER
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Patent number: 10394733Abstract: A data processing apparatus includes a number of processor cores, a shared processor cache, a bus unit and a bus controller. The shared processor cache is connected to each of the processor cores and to a main memory. The bus unit is connected to the shared processor cache by a bus controller for transferring data to/from an I/O device. In order to achieve further improvements to the data transfer rate between the processor cache and I/O devices, the bus controller is configured, in response to receiving a descriptor from a processor core, to perform a direct memory access to the shared processor cache for transferring data according to the descriptor from the shared processor cache to the I/O device via the bus unit.Type: GrantFiled: July 27, 2017Date of Patent: August 27, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Norbert Hagspiel, Sascha Junghans, Matthias Klein, Joerg Walter
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Publication number: 20190094300Abstract: It is determined, if a simulated hardware signal of a design for an electronic circuit has an influence on a checker for simulation errors. To achieve this, a checker control flow database is generated for a static code description containing checkers and concerned simulated signals. Further, a database based on the output of instrumented verification code is generated, thus gaining dynamic information about the verification code. Herein, the hardware signal values will be associated with colored values or, alternatively, attributed values. For the checkers in the checker control flow database, a list of attributes is generated and stored. Based on the above operations, a hardware signal database is generated, wherein hardware signals are mapped to a list of checkers, based on determining, for each checker in the checker database, the associated hardware signals from its list of attributed values.Type: ApplicationFiled: November 8, 2017Publication date: March 28, 2019Inventors: Carsten Greiner, Minh Cuong Tran, Gerrit Koch, Joerg Walter
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Publication number: 20190094299Abstract: It is determined, if a simulated hardware signal of a design for an electronic circuit has an influence on a checker for simulation errors. To achieve this, a checker control flow database is generated for a static code description containing checkers and concerned simulated signals. Further, a database based on the output of instrumented verification code is generated, thus gaining dynamic information about the verification code. Herein, the hardware signal values will be associated with colored values or, alternatively, attributed values. For the checkers in the checker control flow database, a list of attributes is generated and stored. Based on the above operations, a hardware signal database is generated, wherein hardware signals are mapped to a list of checkers, based on determining, for each checker in the checker database, the associated hardware signals from its list of attributed values.Type: ApplicationFiled: September 25, 2017Publication date: March 28, 2019Inventors: Carsten Greiner, Minh Cuong Tran, Gerrit Koch, Joerg Walter
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Patent number: 10229035Abstract: Generating instructions, in particular for mailbox verification in a simulation environment. A sequence of instructions is received, as well as selection data representative of a plurality of commands including a special command. Repeatedly selecting one of the plurality of commands and outputting an instruction based on the selected command. The outputting of an instruction includes outputting a next instruction in the sequence of instructions if the selected command is the special command, and outputting an instruction associated with the command if the selected command is not the special command.Type: GrantFiled: November 9, 2017Date of Patent: March 12, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Joerg Deutschle, Ursel Hahn, Joerg Walter, Ernst-Dieter Weissenberger
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Publication number: 20190073291Abstract: Generating instructions, in particular for mailbox verification in a simulation environment. A sequence of instructions is received, as well as selection data representative of a plurality of commands including a special command. Repeatedly selecting one of the plurality of commands and outputting an instruction based on the selected command. The outputting of an instruction includes outputting a next instruction in the sequence of instructions if the selected command is the special command, and outputting an instruction associated with the command if the selected command is not the special command.Type: ApplicationFiled: November 6, 2018Publication date: March 7, 2019Inventors: Joerg DEUTSCHLE, Ursel HAHN, Joerg WALTER, Ernst-Dieter WEISSENBERGER
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Patent number: 10007625Abstract: According to embodiments of the invention, methods, computer system, and apparatus for virtual channel management and bus multiplexing are disclosed. The method may include establishing a virtual channel from a first device to a second device via a bus, the bus having a first bus capacity and a second bus capacity, the second bus capacity having greater capacity than the first bus capacity, determining whether a store command is issued for the first bus capacity, determining whether the first bus capacity is available, and allocating the second bus capacity and marking the second bus capacity as unavailable in response to the store command if the first bus capacity is unavailable.Type: GrantFiled: October 29, 2015Date of Patent: June 26, 2018Assignee: International Business Machines CorporationInventors: Norbert Hagspiel, Sascha Junghans, Matthias Klein, Joerg Walter
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Publication number: 20180121296Abstract: Automatically configuring backup client systems and backup server systems in a backup environment includes the following steps: determining if a new backup client system is available in the backup environment; in case of an available new backup client system a backup configuration module performs the sub-steps of: determining data types the new backup client system has to backup; determining corresponding backup policies for the determined data types based on a backup policy table mapping data types with backup policies; selecting a backup server system for the determined data types based on a backup server table including connection details of available backup server systems; configuring the determined backup policies for the data types of the new backup client system on the selected backup server systems; and updating the backup server table with an identifier of the new backup client system and an identifier of the backup policy.Type: ApplicationFiled: December 27, 2017Publication date: May 3, 2018Inventors: Andre Gaschler, Nils Haustein, Dominic Mueller-Wicke, Tim U. Scheideler, Joerg Walter
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Patent number: 9916268Abstract: A data processing apparatus includes a number of processor cores, a shared processor cache, a bus unit and a bus controller. The shared processor cache is connected to each of the processor cores and to a main memory. The bus unit is connected to the shared processor cache by a bus controller for transferring data to/from an I/O device. In order to achieve further improvements to the data transfer rate between the processor cache and I/O devices, the bus controller is configured, in response to receiving a descriptor from a processor core, to perform a direct memory access to the shared processor cache for transferring data according to the descriptor from the shared processor cache to the I/O device via the bus unit.Type: GrantFiled: November 24, 2014Date of Patent: March 13, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Norbert Hagspiel, Sascha Junghans, Matthias Klein, Joerg Walter
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Publication number: 20180067840Abstract: Generating instructions, in particular for mailbox verification in a simulation environment. A sequence of instructions is received, as well as selection data representative of a plurality of commands including a special command. Repeatedly selecting one of the plurality of commands and outputting an instruction based on the selected command. The outputting of an instruction includes outputting a next instruction in the sequence of instructions if the selected command is the special command, and outputting an instruction associated with the command if the selected command is not the special command.Type: ApplicationFiled: November 9, 2017Publication date: March 8, 2018Inventors: Joerg DEUTSCHLE, Ursel HAHN, Joerg WALTER, Ernst-Dieter WEISSENBERGER
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Patent number: 9904616Abstract: Generating instructions, in particular for mailbox verification in a simulation environment. A sequence of instructions is received, as well as selection data representative of a plurality of commands including a special command. Repeatedly selecting one of the plurality of commands and outputting an instruction based on the selected command. The outputting of an instruction includes outputting a next instruction in the sequence of instructions if the selected command is the special command, and outputting an instruction associated with the command if the selected command is not the special command.Type: GrantFiled: November 1, 2012Date of Patent: February 27, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Joerg Deutschle, Ursel Hahn, Joerg Walter, Ernst-Dieter Weissenberger
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Patent number: 9892003Abstract: Automatically configuring backup client systems and backup server systems in a backup environment includes the following steps: determining if a new backup client system is available in the backup environment; in case of an available new backup client system a backup configuration module performs the sub-steps of: determining data types the new backup client system has to backup; determining corresponding backup policies for the determined data types based on a backup policy table mapping data types with backup policies; selecting a backup server system for the determined data types based on a backup server table including connection details of available backup server systems; configuring the determined backup policies for the data types of the new backup client system on the selected backup server systems; and updating the backup server table with an identifier of the new backup client system and an identifier of the backup policy.Type: GrantFiled: February 11, 2015Date of Patent: February 13, 2018Assignee: International Business Machines CorporationInventors: Andre Gaschler, Nils Haustein, Dominic Mueller-Wicke, Tim U. Scheideler, Joerg Walter
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Publication number: 20170322896Abstract: A data processing apparatus includes a number of processor cores, a shared processor cache, a bus unit and a bus controller. The shared processor cache is connected to each of the processor cores and to a main memory. The bus unit is connected to the shared processor cache by a bus controller for transferring data to/from an I/O device. In order to achieve further improvements to the data transfer rate between the processor cache and I/O devices, the bus controller is configured, in response to receiving a descriptor from a processor core, to perform a direct memory access to the shared processor cache for transferring data according to the descriptor from the shared processor cache to the I/O device via the bus unit.Type: ApplicationFiled: July 27, 2017Publication date: November 9, 2017Inventors: Norbert HAGSPIEL, Sascha JUNGHANS, Matthias KLEIN, Joerg WALTER
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Patent number: 9767048Abstract: A data processing system is provided which includes a processor nest communicatively coupled to an input/output bus by a bus controller, and a service interface controller communicatively coupled to the processor nest. The system includes storage for storing commands for the bus controller and associated command data and resulting status data, the storage being communicatively coupled to the processor nest and the bus controller. The service interface controller is configured, in response to received service commands, to read and write the storage, to execute the command specified in the storage, to retrieve the result of the command, and to store the result in the storage.Type: GrantFiled: September 23, 2015Date of Patent: September 19, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Norbert Hagspiel, Sascha Junghans, Matthias Klein, Joerg Walter