Patents by Inventor Joerg Wohlfahrt
Joerg Wohlfahrt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7187602Abstract: Memory reliability is improved by using redundancy to repair errors detected by ECC. In one embodiment, redundancy repairs errors which cannot be corrected by ECC. The redundancy can employ the use of electronic fuses, enabling repairs after an IC containing the memory is packaged. Redundancy can also be performed prior to packaging of the IC.Type: GrantFiled: June 13, 2003Date of Patent: March 6, 2007Assignee: Infineon Technologies AktiengesellschaftInventors: Joerg Wohlfahrt, Thomas Roehr, Michael Jacob
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Patent number: 7003432Abstract: A method of analyzing cells of a memory device is disclosed. Generally, a plurality of fail signatures is generated, wherein each fail signature is associated with a type of failure. Voltages according to a plurality of test patterns are applied to nodes of a cell of the memory device. Fail data of the cell for the plurality of patterns is then analyzed, and a fail signature of the cell is determined. A type of failure of the cell based upon the plurality of fail signatures is then determined. A system for analyzing cells of a memory device is also disclosed. The system generally includes a plurality of probes applying different voltages to a cell of the memory device. A control circuit varies the voltages applied to the cell, and compares the failures of the cell as the test voltage applied to the cell is varied to an artificial bit map. Finally, an output device generates an output indicating a type of failure of the cell.Type: GrantFiled: December 30, 2003Date of Patent: February 21, 2006Assignee: Infineon Technologies Richmond LPInventors: Joerg Wohlfahrt, Thomas Hladschik, Jens Holzhaeuser, Dieter Rathei
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Patent number: 6999887Abstract: A memory cell signal window testing apparatus 101 and method for testing the signal window of a memory are disclosed. First data is written to a memory cell during a write cycle. A low cell signal is read from the memory cell during a first read cycle. A comparison is made between the low signal and a low reference signal. The result of the comparison is stored in a first storage register. Second data is then written to the memory cell during a write cycle. A high cell signal is read from the memory cell during a second read cycle. A comparison is made between the high cell signal and a high reference signal. The result of the comparison is stored in a second storage register. The results in the first and second storage registers are compared and an output is provided indicating that the memory cell has failed the test if the comparison shows that both the low cell signal is higher than the low reference signal and the high cell signal is lower than the high reference signal.Type: GrantFiled: August 6, 2003Date of Patent: February 14, 2006Assignee: Infineon Technologies AGInventors: Norbert Rehm, Hans-Oliver Joachim, Michael Jacob, Joerg Wohlfahrt
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Patent number: 6963813Abstract: A method for classifying patterns of failcodes on a semiconductor wafer, in accordance with the present invention, includes determining failcodes for chips on the wafer and checking adjacent chips for each chip on the wafer having a failcode to determine a failcode pattern having a defined number of chips.Type: GrantFiled: September 13, 2000Date of Patent: November 8, 2005Inventors: Dieter Rathei, Peter Oswald, Thomas Hladschik, Joerg Wohlfahrt
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Publication number: 20050149285Abstract: A method of analyzing cells of a memory device is disclosed. The method generally comprises steps of establishing a plurality of fail signatures, wherein each fail signature is associated with a type of failure. Voltages according to a plurality of test patterns are applied to nodes of a cell of the memory device. Fail data of the cell for the plurality of patterns is then analyzed, and a fail signature of the cell is determined. A type of failure of the cell based upon the plurality of fail signatures is then determined. A system for analyzing cells of a memory device is also disclosed. The system preferably comprises a plurality of probes applying different voltages to a cell of the memory device. A control circuit varies the voltages applied to the cell, and compares the failures of the cell as the test voltage applied to the cell is varied to an artificial bit map. Finally, an output device generates an output indicating a type of failure of the cell.Type: ApplicationFiled: December 30, 2003Publication date: July 7, 2005Inventors: Joerg Wohlfahrt, Thomas Hladschik, Jens Holzhaeuser, Dieter Rathei
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Patent number: 6903959Abstract: A memory IC having improved sensing during reads is disclosed. The IC includes the use of first and second reference voltages for sensing to compensate for asymmetry that exists between cells on bitline true and bitline complement. The first reference voltage is used for sensing a cell on bitline true while the second reference voltage is used for sensing a cell on bitline complement.Type: GrantFiled: September 24, 2002Date of Patent: June 7, 2005Assignee: Infineon Technologies AktiengesellschaftInventors: Thomas Roehr, Hans-Oliver Joachim, Joerg Wohlfahrt, Norbert Rehm
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Patent number: 6885597Abstract: A test circuit for testing differential read signals during a memory access is disclosed. The test circuit is coupled to a pair of bit lines. During a read access, a selected memory cell produces a differential read signal on the bit lines. When the test circuit is activated, the magnitude of the differential read signal is varied. This enables easy testing of read signal margins in, for example, memory ICs.Type: GrantFiled: September 10, 2002Date of Patent: April 26, 2005Assignees: Infineon Technologies Aktiengesellschaft, Kabushiki Kaisha ToshibaInventors: Thomas Roehr, Hans-Oliver Joachim, Michael Jacob, Joerg Wohlfahrt, Takashima Daisaburo
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Publication number: 20050063212Abstract: A semiconductor memory comprises a first capacitor for storing digital data connecting a cell plate line to a first bit-line through a first select transistor. The first select transistor is activated through a connection to a word line. At least one reference capacitor provides a reference voltage to a reference bit-line. A sense amplifier connected to the first and reference bit-lines measures a differential read signal on the first and reference bit-lines. A toggle flip flop alternately changes the polarization of charge stored on the reference capacitors.Type: ApplicationFiled: September 18, 2003Publication date: March 24, 2005Inventors: Michael Jacob, Norbert Rehm, Hans-Oliver Joachim, Joerg Wohlfahrt
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Publication number: 20050033541Abstract: A memory cell signal window testing apparatus 101 and method for testing the signal window of a memory are disclosed. First data is written to a memory cell during a write cycle. A low cell signal is read from the memory cell during a first read cycle. A comparison is made between the low signal and a low reference signal. The result of the comparison is stored in a first storage register. Second data is then written to the memory cell during a write cycle. A high cell signal is read from the memory cell during a second read cycle. A comparison is made between the high cell signal and a high reference signal. The result of the comparison is stored in a second storage register. The results in the first and second storage registers are compared and an output is provided indicating that the memory cell has failed the test if the comparison shows that both the low cell signal is higher than the low reference signal and the high cell signal is lower than the high reference signal.Type: ApplicationFiled: August 6, 2003Publication date: February 10, 2005Inventors: Norbert Rehm, Hans-Oliver Joachim, Michael Jacob, Joerg Wohlfahrt
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Patent number: 6826099Abstract: A semiconductor memory test mode configuration includes a first capacitor for storing digital data. The first capacitor connects a cell plate line to a first bit line through a first select transistor which is activated through a connection to a word line. A second capacitor for storing digital data connects the cell plate line to a second bit line through a second select transistor which is also activated through a connection to the word line. A sense amplifier is connected to the first and second bit lines for measuring a differential read signal on the first and second bit lines. A constant current mover, for example a constant current sink or source, is connected to the first bit line through a third transistor for changing the amount of charge on the first bit line when the third transistor is turned on to reduce the differential read signal.Type: GrantFiled: November 20, 2002Date of Patent: November 30, 2004Assignee: Infineon Technologies AGInventors: Hans-Oliver Joachim, Thomas Roehr, Joerg Wohlfahrt
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Publication number: 20040232457Abstract: An IC with a memory array having a series architecture is disclosed. A memory cell of a series group comprises a transistor coupled to a capacitor in parallel. The capacitor includes first and second subcapacitors, one stacked one on top of the other. Providing a capacitor with two,or more subcapacitors in a stack advantageously increases the capacitance of a capacitor without increasing surface area.Type: ApplicationFiled: December 30, 2002Publication date: November 25, 2004Inventors: Joerg Wohlfahrt, Rainer Bruchhaus, Andreas Hilliger
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Publication number: 20040208043Abstract: A FeRAM memory chip comprises an array 5 of non-volatile ferrocapacitor memory cells for storing data. Input pins receive data to be stored, and address data indicating where in the array of memory cells the data should be stored. The FeRAM memory chip further has a reset unit 7 for recognising an externally applied reset signal. The reset unit 7, upon recognition of the reset signal, initiates a reset operation in which at least a portion of the data stored in the memory cells is set to predetermined values.Type: ApplicationFiled: April 17, 2003Publication date: October 21, 2004Inventors: Joerg Wohlfahrt, Hans-Oliver Joachim
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Patent number: 6807084Abstract: A FeRAM memory chip comprises an array 5 of non-volatile ferrocapacitor memory cells for storing data. Input pins receive data to be stored, and address data indicating where in the array of memory cells the data should be stored. The FeRAM memory chip further has a reset unit 7 for recognizing an externally applied reset signal. The reset unit 7, upon recognition of the reset signal, initiates a reset operation in which at least a portion of the data stored in the memory cells is set to predetermined values.Type: GrantFiled: April 17, 2003Date of Patent: October 19, 2004Assignee: Infineon Technologies AGInventors: Joerg Wohlfahrt, Hans-Oliver Joachim
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Patent number: 6800890Abstract: An IC with a memory array having a series architecture is disclosed. A memory cell of a series group comprises a transistor coupled to a capacitor in parallel. The capacitor includes first and second subcapacitors, one stacked one on top of the other. Providing a capacitor with two or more subcapacitors in a stack advantageously increases the capacitance of a capacitor without increasing surface area.Type: GrantFiled: December 30, 2002Date of Patent: October 5, 2004Assignee: Infineon Technologies AktiengesellschaftInventors: Joerg Wohlfahrt, Rainer Bruchhaus, Andreas Hilliger
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Publication number: 20040095820Abstract: The present invention provides a test mode section for facilitating a worst case product test sequence for signal margin to ensure full product functionality over the entire component lifetime taking all aging effects into account A semiconductor memory test mode configuration includes a first capacitor for storing digital data connecting a cell plate line to a first bit line through a first select transistor. The first select transistor is activated through a connection to a word line. A second capacitor stores digital data and connects the cell plate line to a second bit line through a second select transistor. The second select transistor is activated through a connection to the word line. A sense amplifier is connected to the first and second bit lines for measuring a differential read signal on the first and second bit lines.Type: ApplicationFiled: November 20, 2002Publication date: May 20, 2004Inventors: Michael Jacob, Joerg Wohlfahrt, Thomas Roehr, Nobert Rehm
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Publication number: 20040095819Abstract: The present invention provides a test mode section for facilitating a worst case product test sequence for signal margin to ensure full product functionality over the entire component lifetime taking all aging effects into account. A semiconductor memory test mode configuration includes a first capacitor for storing digital data. The first capacitor connects a cell plate line to a first bit line through a first select transistor. The first select transistor is activated through a connection to a word line. A second capacitor for storing digital data connects the cell plate line to a second bit line through a second select transistor. The second select transistor is also activated through a connection to the word line. A sense amplifier is connected to the first and second bit lines for measuring a differential read signal on the first and second bit lines.Type: ApplicationFiled: November 20, 2002Publication date: May 20, 2004Inventors: Hans-Oliver Joachim, Thomas Roehr, Joerg Wohlfahrt
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Publication number: 20040095799Abstract: The present invention provides a test mode section for facilitating a worst case product test sequence for signal margin to ensure full product functionality over the entire component lifetime taking all aging effects into account. A semiconductor memory test mode configuration includes a first capacitor for storing digital data The capacitor connects a cell plate line to a first bit line through a first select transistor. The first select transistor is activated through a connection to a word line. A second capacitor stores digital data and connects the cell plate line to a second bit line through a second select transistor. The second select transistor is also activated through a connection to the word line. A sense amplifier is connected to the first and second bit lines and measures a differential read signal on the first and second bit lines.Type: ApplicationFiled: November 20, 2002Publication date: May 20, 2004Inventors: Michael Jacob, Thomas Roehr, Joerg Wohlfahrt, Hans-Oliver Joachim
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Publication number: 20040095798Abstract: An improved architecture which reduces the adverse impact of the disturb pulse on non-selected ferroelectric memory cells is disclosed. The architecture provides plateline selection switches for selectively coupling memory groups on the selected side of the memory block to the plateline and decoupling the non-selected side of the memory block from the plateline. By decoupling the non-selected side of the memory block from the plateline, the plate pulse does not adversely affect the memory cells in the non-selected side of the memory block.Type: ApplicationFiled: September 19, 2002Publication date: May 20, 2004Inventors: Joerg Wohlfahrt, Michael Jacob, Thomas Roehr
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Patent number: 6731529Abstract: A memory chain with capacitors having different capacitances, depending on the location of the memory cell within the chain, is described. Varying the capacitances of the capacitors advantageously enables an effective capacitance for all memory cells within the chain to be about the same.Type: GrantFiled: June 4, 2002Date of Patent: May 4, 2004Assignees: Infineon Technologies Aktiengesellschaft, Kabushiki Kaisha ToshibaInventors: Michael Jacob, Joerg Wohlfahrt, Norbert Rehm, Daisaburo Takashima
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Patent number: 6731554Abstract: The present invention provides a test mode section for facilitating a worst case product test sequence for signal margin to ensure full product functionality over the entire component lifetime taking all aging effects into account. A semiconductor memory test mode configuration includes a first capacitor for storing digital data connecting a cell plate line to a first bit line through a first select transistor. The first select transistor is activated through a connection to a word line. A second capacitor stores digital data and connects the cell plate line to a second bit line through a second select transistor. The second select transistor is activated through a connection to the word line.Type: GrantFiled: November 20, 2002Date of Patent: May 4, 2004Assignee: Infineon Technologies AGInventors: Michael Jacob, Joerg Wohlfahrt, Thomas Roehr, Nobert Rehm