Abstract: The present invention relates to a receiver circuit for processing an incoming bit stream from a bus system. The circuit comprises an analog interface for converting the analog signal to a digital input data stream. The interface comprises an analog filter and a switch to process the analog signal before generating the digital input data stream using the filter if, and only if, a selection criterion controlling the switch is met. The circuit comprises a frame decoding unit for decoding a data frame encoded in the digital input data stream in accordance with a CAN protocol, and a frame processing unit that comprises a flexible data rate detector and a recessive bit counter for counting consecutive recessive bits after detecting the flexible data rate frame. The selection criterion is satisfied when the flexible data rate frame is detected and unsatisfied when the recessive bit counter reaches a predetermined number.

Abstract: A system having a plurality of devices configured in a daisy chain network including a communication bus connecting the devices and adapted to exchange address-setting information. Each device includes an input pin adapted to receive via an input signal line different from the communication bus a signal comprising configuration information for configuring at least the device; a configuration handling unit adapted to detect a configuration mode and to configure the device according to the configuration information; an indicator adapted to indicate whether the configuration handling unit has finished configuring the device; an output pin adapted to forward the configuration information to the daisy chain network when the indicator indicates the configuration of the device is done; and a safety handling unit adapted to be operable in a safety handling mode when the indicator indicates the configuration of the device is done.

Abstract: The present invention relates to a receiver circuit for processing an incoming bit stream from a bus system. The circuit comprises an analog interface for converting the analog signal to a digital input data stream. The interface comprises an analog filter and a switch to process the analog signal before generating the digital input data stream using the filter if, and only if, a selection criterion controlling the switch is met. The circuit comprises a frame decoding unit for decoding a data frame encoded in the digital input data stream in accordance with a CAN protocol, and a frame processing unit that comprises a flexible data rate detector and a recessive bit counter for counting consecutive recessive bits after detecting the flexible data rate frame. The selection criterion is satisfied when the flexible data rate frame is detected and unsatisfied when the recessive bit counter reaches a predetermined number.

Abstract: A transceiver circuit for communicating data over a CAN bus having a first and second bus line the transceiver circuit comprising: a data input port, a data output port, a CAN-bus transceiver unit having a receive data output port for providing data received from the CAN-bus, and a transmit data input port for receiving data to be transmitted to the CAN-bus; a control input port for receiving a control signal indicative of whether transmission of data from this transceiver circuit to the CAN-bus is allowed or prohibited; a filtering circuit adapted for filtering the control signal received on the control input port and for providing a filtered control signal; a logic circuitry adapted for configuring the CAN-bus transceiver unit in receive mode based on the debounced control signal irrespective of ongoing communication on the CAN-bus.

Abstract: A system having a plurality of devices configured in a daisy chain network including a communication bus connecting the devices and adapted to exchange address-setting information. Each device includes an input pin adapted to receive via an input signal line different from the communication bus a signal comprising configuration information for configuring at least the device; a configuration handling unit adapted to detect a configuration mode and to configure the device according to the configuration information; an indicator adapted to indicate whether the configuration handling unit has finished configuring the device; an output pin adapted to forward the configuration information to the daisy chain network when the indicator indicates the configuration of the device is done; and a safety handling unit adapted to be operable in a safety handling mode when the indicator indicates the configuration of the device is done.

Abstract: A circuit for receiving and processing a bit stream obtained from an electronic communication bus-system comprises a bit stream processor and bit sampling of the bit stream to provide a sampled output signal. The circuit comprises a frame decoder for decoding a data frame encoded in the sampled output signal, and a clock signal generator for generating a first clock signal for the bit stream processor. The circuit comprises a clock signal downsampler for generating a second clock signal having a lower frequency than the first clock signal, in which the second clock signal is based on a co-occurrence of a clock pulse in the first clock signal and the emission of a bit in the sampled output signal. The bit stream processor is adapted for synchronizing the first clock signal to an external protocol timing of the incoming bit stream.

Abstract: A circuit for receiving and processing a bit stream obtained from an electronic communication bus-system comprises a bit stream processor and bit sampling of the bit stream to provide a sampled output signal. The circuit comprises a frame decoder for decoding a data frame encoded in the sampled output signal, and a clock signal generator for generating a first clock signal for the bit stream processor. The circuit comprises a clock signal downsampler for generating a second clock signal having a lower frequency than the first clock signal, in which the second clock signal is based on a co-occurrence of a clock pulse in the first clock signal and the emission of a bit in the sampled output signal. The bit stream processor is adapted for synchronizing the first clock signal to an external protocol timing of the incoming bit stream.

Abstract: A transceiver circuit for communicating data over a CAN bus having a first and second bus line the transceiver circuit comprising: a data input port, a data output port, a CAN-bus transceiver unit having a receive data output port for providing data received from the CAN-bus, and a transmit data input port for receiving data to be transmitted to the CAN-bus; a control input port for receiving a control signal indicative of whether transmission of data from this transceiver circuit to the CAN-bus is allowed or prohibited; a filtering circuit adapted for filtering the control signal received on the control input port and for providing a filtered control signal; a logic circuitry adapted for configuring the CAN-bus transceiver unit in receive mode based on the debounced control signal irrespective of ongoing communication on the CAN-bus.

Abstract: A method for a power optimal control of a BLDC motor by continuously updated commutation points and circuit assembly for a power optimal control of a BLDC motor. The method includes measuring a time difference (?T) between two immediately subsequent zero crossings (TN1, TN2) of first and second motor phases, and performing a commutation of an immediately next motor phase after substantially one-half of the time difference (?T/2) elapses after the zero crossing of the second motor phase (TN2). The commutation is performed for all phases in a continuous manner in accordance with a switching algorithm (Tcommutation=TN2+(?T/2)).

Abstract: A method for a power optimal control of a BLDC motor by continuously updated commutation points and circuit assembly for a power optimal control of a BLDC motor. The method includes measuring a time difference (?T) between two immediately subsequent zero crossings (TN1, TN2) of first and second motor phases, and performing a commutation of an immediately next motor phase after substantially one-half of the time difference (?T/2) elapses after the zero crossing of the second motor phase (TN2). The commutation is performed for all phases in a continuous manner in accordance with a switching algorithm (Tcommutation=TN2+(?T/2)).