Patents by Inventor Joeri De Vos
Joeri De Vos has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11769750Abstract: A substrate, assembly and method for bonding and electrically interconnecting substrates are provided. According to the method, two substrates are provided, each comprising metal contact structures that are electrically isolated from each other by a bonding layer of dielectric material. Openings are produced in the bonding layer, the openings lying within the surface area of the respective contact structures, exposing the contact material of the structures at the bottom of the openings. Then a layer of conductive material is deposited, filling the openings, after which the material is planarized, removing it from the surface of the bonding layer and leaving a recessed contact patch in the openings. The substrates are then aligned, brought into contact, and bonded by applying an annealing step at a temperature suitable for causing thermal expansion of the contact structures.Type: GrantFiled: July 28, 2021Date of Patent: September 26, 2023Assignee: Imec VZWInventors: Joeri De Vos, Eric Beyne
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Publication number: 20220037283Abstract: A substrate, assembly and method for bonding and electrically interconnecting substrates are provided. According to the method, two substrates are provided, each comprising metal contact structures that are electrically isolated from each other by a bonding layer of dielectric material. Openings are produced in the bonding layer, the openings lying within the surface area of the respective contact structures, exposing the contact material of the structures at the bottom of the openings. Then a layer of conductive material is deposited, filling the openings, after which the material is planarized, removing it from the surface of the bonding layer and leaving a recessed contact patch in the openings. The substrates are then aligned, brought into contact, and bonded by applying an annealing step at a temperature suitable for causing thermal expansion of the contact structures.Type: ApplicationFiled: July 28, 2021Publication date: February 3, 2022Inventors: Joeri De Vos, Eric Beyne
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Patent number: 10170450Abstract: A method for bonding and interconnecting two or more IC devices arranged on substrates such as silicon wafers is disclosed. In one aspect, the wafers are bonded by a direct bonding technique to form a wafer assembly, and the multiple IC devices are provided with metal contact structures. At least the upper substrate is provided prior to bonding with a cavity in its bonding surface. A TSV (Through Semiconductor Via) is produced through the bonded wafer assembly and an aggregate opening is formed including the TSV opening and the cavity. After the formation of an isolation liner on at least part of the sidewalls of the aggregate opening (that is, at least on the part where the liner isolates the aggregate opening from semiconductor material), a TSV interconnection plug is produced in the aggregate opening.Type: GrantFiled: September 6, 2017Date of Patent: January 1, 2019Assignee: IMEC vzwInventors: Eric Beyne, Joeri De Vos, Stefaan Van Huylenbroeck
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Patent number: 10066303Abstract: The invention relates to a substrate having at least one main surface comprising at least one non-noble metallic bonding landing pad covered by a capping layer thereby shielding the non-noble metallic bonding landing pad from the environment. This capping layer comprises an alloy, the alloy being NiB or CoB and containing an atomic concentration percentage of boron in the range of 10% to 50%.Type: GrantFiled: February 27, 2015Date of Patent: September 4, 2018Assignees: IMEC VZW, GLOBALFOUNDRIES INC.Inventors: Eric Beyne, Joeri De Vos, Jaber Derakhshandeh, Luke England, George Vakanas
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Publication number: 20180068984Abstract: A method for bonding and interconnecting two or more IC devices arranged on substrates such as silicon wafers is disclosed. In one aspect, the wafers are bonded by a direct bonding technique to form a wafer assembly, and the multiple IC devices are provided with metal contact structures. At least the upper substrate is provided prior to bonding with a cavity in its bonding surface. A TSV (Through Semiconductor Via) is produced through the bonded wafer assembly and an aggregate opening is formed including the TSV opening and the cavity. After the formation of an isolation liner on at least part of the sidewalls of the aggregate opening (that is, at least on the part where the liner isolates the aggregate opening from semiconductor material), a TSV interconnection plug is produced in the aggregate opening.Type: ApplicationFiled: September 6, 2017Publication date: March 8, 2018Inventors: Eric Beyne, Joeri De Vos, Stefaan Van Huylenbroeck
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Publication number: 20150247244Abstract: The invention relates to a substrate having at least one main surface comprising at least one non-noble metallic bonding landing pad covered by a capping layer thereby shielding the non-noble metallic bonding landing pad from the environment. This capping layer comprises an alloy, the alloy being NiB or CoB and containing an atomic concentration percentage of boron in the range of 10% to 50%.Type: ApplicationFiled: February 27, 2015Publication date: September 3, 2015Inventors: Eric Beyne, Joeri De Vos, Jaber Derakhshandeh, Luke England, George Vakanas
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Patent number: 8530264Abstract: Methods of fabricating complementary metal-oxide-semiconductor (CMOS) imagers for backside illumination are disclosed. In one embodiment, the method may include forming at a front side of a substrate a plurality of high aspect ratio trenches having a predetermined trench depth, and forming at the front side of the substrate a plurality of photodiodes, where each photodiode is adjacent at least one trench. The method may further include forming an oxide layer on inner walls of each trench, removing the oxide layer, filling each trench with a highly doped material, and thinning the substrate from a back side opposite the front side to a predetermined final substrate thickness. In some embodiments, the substrate may have a predetermined doping profile, such as a graded doping profile, that provides a built-in electric field suitable to guide the flow of photogenerated minority carriers towards the front side.Type: GrantFiled: August 1, 2011Date of Patent: September 10, 2013Assignee: IMECInventors: Koen De Munck, Kiki Minoglou, Joeri De Vos
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Patent number: 8493736Abstract: The present disclosure is related to a device for cooling the surface of a semiconductor device such as an integrated circuit or the like, the cooling device comprising a plurality of channels (3?) which are non-parallel to the surface to be cooled, each channel comprising a plurality of separate electrodes (5) or equivalent conducting areas arranged along the length of each channel, the device further comprising or being connectable to means for applying a voltage to the electrodes or conducting areas in each channel according to a sequence, the sequence being such that a droplet (6) of cooling liquid in a channel may be moved from one electrode to the next, thereby transporting the droplet from the top of the channel to the bottom, from where the droplet impinges on the surface to be cooled.Type: GrantFiled: June 1, 2011Date of Patent: July 23, 2013Assignee: IMECInventors: Herman Oprins, Bart Vandevelde, Paolo Fiorini, Eric Beyne, Joeri De Vos, Bivragh Majeed
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Publication number: 20120028401Abstract: Methods of fabricating complementary metal-oxide-semiconductor (CMOS) imagers for backside illumination are disclosed. In one embodiment, the method may include forming at a front side of a substrate a plurality of high aspect ratio trenches having a predetermined trench depth, and forming at the front side of the substrate a plurality of photodiodes, where each photodiode is adjacent at least one trench. The method may further include forming an oxide layer on inner walls of each trench, removing the oxide layer, filling each trench with a highly doped material, and thinning the substrate from a back side opposite the front side to a predetermined final substrate thickness. In some embodiments, the substrate may have a predetermined doping profile, such as a graded doping profile, that provides a built-in electric field suitable to guide the flow of photogenerated minority carriers towards the front side.Type: ApplicationFiled: August 1, 2011Publication date: February 2, 2012Applicant: IMECInventors: Koen De Munck, Kiki Minoglou, Joeri De Vos
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Publication number: 20110304987Abstract: The present disclosure is related to a device for cooling the surface of a semiconductor device such as an integrated circuit or the like, the cooling device comprising a plurality of channels (3?) which are non-parallel to the surface to be cooled, each channel comprising a plurality of separate electrodes (5) or equivalent conducting areas arranged along the length of each channel, the device further comprising or being connectable to means for applying a voltage to the electrodes or conducting areas in each channel according to a sequence, the sequence being such that a droplet (6) of cooling liquid in a channel may be moved from one electrode to the next, thereby transporting the droplet from the top of the channel to the bottom, from where the droplet impinges on the surface to be cooled.Type: ApplicationFiled: June 1, 2011Publication date: December 15, 2011Applicant: IMECInventors: Herman Oprins, Bart Vandevelde, Paolo Fiorini, Eric Beyne, Joeri De Vos, Bivragh Majeed