Abstract: A phase-locked loop for a differential recovery of the clock signal wherein an extracted data signal (DS) is conveyed via a phase delay element and thence to a phase comparator. In the phase comparator comparison signals, whose phase shifts can be set relative to one another, differential phase evaluation is carried out. This results in a control signal (RS) whose operating point, independent of the power of the transmit channel, always lies in the center of the control range. In the inventive differential timing recovery, the dependencies on power fluctuations, signal-to-noise ratio, the pulse shape and on transmitted bit patterns are eliminated to the greatest possible extent.