Abstract: A apparatus is provided for buffering data between a memory controller and a DRAM. The apparatus includes a phase locked loop (PLL), a phase interpolator for aligning a phase of an output clock signal in response to a phase aligning control word, and a non-volatile storage location permanently storing the phase aligning control word. The phase aligning control word is determined through an initial training procedure of the device under predetermined training conditions of at least a supply voltage level and a temperature, and the predetermined training conditions are set so as to optimize the phase alignment of an edge of the output clock signal with respect to the buffered data signal.

Abstract: An integrated CMOS clock generator with a self-biased phase locked loop circuit comprises a phase-frequency detector with a reference signal input, a feedback signal input and an output. A first charge pump of the clock generator has an input connected to the output of the phase-frequency detector and an output that supplies a control voltage. A loop capacitor is connected to the output of the first charge pump. The clock generator further has a second charge pump with an input connected to the output of the phase-frequency detector and an output. In particular, the clock generator has two oscillator blocks.

Abstract: A apparatus is provided for buffering data between a memory controller and a DRAM. The apparatus includes a phase locked loop (PLL), a phase interpolator for aligning a phase of an output clock signal in response to a phase aligning control word, and a non-volatile storage location permanently storing the phase aligning control word. The phase aligning control word is determined through an initial training procedure of the device under predetermined training conditions of at least a supply voltage level and a temperature, and the predetermined training conditions are set so as to optimize the phase alignment of an edge of the output clock signal with respect to the buffered data signal.

Abstract: A digital registered data buffer is disclosed that has data paths each with a data input for receiving a digital data input signal (Dn), a clock input for receiving a clock input signal (CLK) and a data output providing a digital data output signal (Qn) for application to a data destination device such as memory devices. The buffer further has a clock output for providing an output clock signal (QCLK) to the data destination device and a phase-locked loop (PLL) with a clock input, a feedback input, a feedback output and a plurality of clock outputs. The buffer uses a pair of data registers, i.e. flip-flops (FF1, FF2) connected in series in each data path. The first data register in each data path is clocked by the clock input signal (CLK) and the second data register in each data path is clocked by one of the clock outputs (PDCLK) from the PLL.

Abstract: A circuit assembly for converting a differential input clock signal pair into a single-ended output clock signal comprises a NMOS differential amplifier (20) including two N-channel field-effect transistors (N1, N2) which converts the input clock signal pair (CLK, NCLK) applied to its differential inputs into a first single-ended signal, a PMOS differential amplifier (22) including two P-channel field-effect transistors (P3, P4) which converts the input clock signal pair applied to its differential inputs into a second single-ended signal, a bias circuit (N5, N6, N7, P5, P6) generating for each differential amplifier a bias voltage defining its working point at which said field-effect transistors (N1, N2; P3, P4) change state as a function of said input clock signal pair (CLK, NCLK), and a NAND circuit (32) for linking said first and said second single-ended signal and outputting the single-ended output clock signal (A-CLK) as the result thereof.

Abstract: An integrated circuit device comprises internally on-chip an oscillator with a signal output. The device has a reference clock input, a first counter with a count input, a control input and a counter output, a second counter with a count input, a control input and an overflow indication output, and a test control logic circuit. The count input of the first counter is connected to the signal output of the oscillator. The count input of the second counter is connected to the reference clock input. The overflow indication output of the second counter is connected to an input of the test control logic circuit. The test control circuit has an output connected to the control input of the first counter to apply a stop counting control signal to the first counter after it has received an overflow indication signal from the second counter. The first counter after it has received a stop counting control signal provides a count at the counter output which is indicative of the output frequency of the oscillator.

Abstract: A digital registered data buffer is disclosed that has data paths each with a data input for receiving a digital data input signal (Dn), a clock input for receiving a clock input signal (CLK) and a data output providing a digital data output signal (Qn) for application to a data destination device such as memory devices. The buffer further has a clock output for providing an output clock signal (QCLK) to the data destination device and a phase-locked loop (PLL) with a clock input, a feedback input, a feedback output and a plurality of clock outputs. The buffer uses a pair of data registers, i.e. flip-flops (FF1, FF2) connected in series in each data path. The first data register in each data path is clocked by the clock input signal (CLK) and the second data register in each data path is clocked by one of the clock outputs (PDCLK) from the PLL.

Abstract: An integrated circuit device comprises internally on-chip an oscillator with a signal output. The device has a reference clock input, a first counter with a count input, a control input and a counter output, a second counter with a count input, a control input and an overflow indication output, and a test control logic circuit. The count input of the first counter is connected to the signal output of the oscillator. The count input of the second counter is connected to the reference clock input. The overflow indication output of the second counter is connected to an input of the test control logic circuit. The test control circuit has an output connected to the control input of the first counter to apply a stop counting control signal to the first counter after it has received an overflow indication signal from the second counter. The first counter after it has received a stop counting control signal provides a count at the counter output which is indicative of the output frequency of the oscillator.

Abstract: An integrated CMOS clock generator with a self-biased phase locked loop circuit comprises a phase-frequency detector with a reference signal input, a feedback signal input and an output. A first charge pump of the clock generator has an input connected to the output of the phase-frequency detector and an output that supplies a control voltage. A loop capacitor is connected to the output of the first charge pump. The clock generator further has a second charge pump with an input connected to the output of the phase-frequency detector and an output. In particular, the clock generator has two oscillator blocks.

Abstract: A circuit assembly for converting a differential input clock signal pair into a single-ended output clock signal comprises a NMOS differential amplifier (20) including two N-channel field-effect transistors (N1, N2) which converts the input clock signal pair (CLK, NCLK) applied to its differential inputs into a first single-ended signal, a PMOS differential amplifier (22) including two P-channel field-effect transistors (P3, P4) which converts the input clock signal pair applied to its differential inputs into a second single-ended signal, a bias circuit (N5, N6, N7, P5, P6) generating for each differential amplifier a bias voltage defining its working point at which said field-effect transistors (N1, N2; P3, P4) change state as a function of said input clock signal pair (CLK, NCLK), and a NAND circuit (32) for linking said first and said second single-ended signal and outputting the single-ended output clock signal (A-CLK) as the result thereof.