Abstract: A method for detecting the presence, and/or determining the location, and/or detecting changes in the material properties, of a first object (4) within a predefined space (12) and compensating for the disturbance caused by a second object, where the method comprises the following steps: providing at least a first and a second electrode (6) capacitively coupled to each other; conductively applying an electrical signal to each of the first and second electrodes (6), the electrical signals being different for the first and second electrodes (6); for each of the electrodes (6) measuring the current signal through, and/or the voltage signal on, the electrode (6); deriving from the measured values an indication of the disturbance caused by the second object; and deriving from the measured values and the indication of the disturbance a disturbance-compensated indication of the presence, and/or the location, and/or changes in the material properties, of the first object (4).

Abstract: Masters request access to a shared resource, such as a shared bus. Usage of the shared bus by each of the masters is monitored, a request to use the shared bus by one of the masters is received, and usage of the shared bus by the master is compared with a corresponding bandwidth threshold. The request is arbitrated if the usage of the shared bus by the master is below the bandwidth threshold, and the request to use the shared bus is granted to the master based on the arbitration.

Abstract: An integrated circuit comprising a plurality of processing cores, characterised by comprising electrically controllable switches for controlling the supply of power to one or more of the processing cores, a memory for saving state data from at least one of the processing cores and a controller adapted to control the supply of power to one or more of the processing cores such that processing cores can be de-powered.

Abstract: A method of decoding data comprising a plurality of data-bursts, comprising the steps of: i) receiving a first one of the data-bursts, ii) associating hypothesis data with the or each received data-bursts; iii) attempting to decode the data; and iv) if the decode is successful to power down the receiver, and if the decode is unsuccessful receiving a further one of the data-bursts and repeating steps ii) to iv), until all of the data has been received.

Abstract: An apparatus includes a first processor that accesses memory according to a first clock frequency, a second processor that accesses memory according to a second clock frequency, and a memory device is configurable to selectively operate according to the first clock frequency or the second clock frequency. A memory controller enables dynamic configuration of organization of the memory device to allow a first portion of the memory device to be accessed by the first processor according to the first clock frequency and a second portion of the memory device to be accessed by the second processor according to the second clock frequency.

Abstract: A method for detecting the presence, and/or determining the location, and/or detecting changes in the material properties, of a first object (4) within a predefined space (12) and compensating for the disturbance caused by a second object, where the method comprises the following steps: providing at least a first and a second electrode (6) capacitively coupled to each other; conductively applying an electrical signal to each of the first and second electrodes (6), the electrical signals being different for the first and second electrodes (6); for each of the electrodes (6) measuring the current signal through, and/or the voltage signal on, the electrode (6); deriving from the measured values an indication of the disturbance caused by the second object; and deriving from the measured values and the indication of the disturbance a disturbance-compensated indication of the presence, and/or the location, and/or changes in the material properties, of the first object (4).

Abstract: Masters request access to a shared resource, such as a shared bus. Usage of the shared bus by each of the masters is monitored, a request to use the shared bus by one of the masters is received, and usage of the shared bus by the master is compared with a corresponding bandwidth threshold. The request is arbitrated if the usage of the shared bus by the master is below the bandwidth threshold, and the request to use the shared bus is granted to the master based on the arbitration.

Abstract: A method of decoding data comprising a plurality of data-bursts, comprising the steps of: i) receiving a first one of the data-bursts, ii) associating hypothesis data with the or each received data-bursts; iii) attempting to decode the data; and iv) if the decode is successful to power down the receiver, and if the decode is unsuccessful receiving a further one of the data-bursts and repeating steps ii) to iv), until all of the data has been received.

Abstract: An integrated circuit comprising a plurality of processing cores, characterised by comprising electrically controllable switches for controlling the supply of power to one or more of the processing cores, a memory for saving state data from at least one of the processing cores and a controller adapted to control the supply of power to one or more of the processing cores such that processing cores can be de-powered.

Abstract: The present invention is directed to methods and apparatus which may be used to help prevent electronic devices, including cell phones, from operating with software copied from (and only authorized for use by or on) another device. A further aspect is a device, including a cell phone, for example, that employs any of such methods and apparatus. Aspects of the present invention compare a program identifier (associated with software stored in a device) to a reference identifier for the device, so as to determine whether the software is authorized for use with that device. Some embodiments respond to the comparison substantially in hardware, so that the software being checked is less able to prevent the device from being disabled in the event that the program identifier and the reference identifier do not match one another.

Abstract: An apparatus is provided for buffering instructions. An instruction store has memory locations for storing instructions. Each instruction can be associated with a timer such that an instruction dispatcher causes the instruction to be sent when the timer indicates that the instruction should be sent.

Abstract: Methods and apparatus are provided for spread spectrum signal processing in a wireless communication system. The apparatus includes a control processor to generate commands for processing spread spectrum signal components and a reconfigurable coprocessor to process the spread spectrum signal components based on the commands and to provide reports to the control processor based on results of processing the signal components.

Abstract: A digital baseband processor is provided which receives a system clock generated by a system oscillator and generates a plurality of clock signals from the system clock. The digital baseband processor includes a digital signal processor for executing digital signal processor instructions, a microcontroller for executing microcontroller instructions, and other modules which may require one of the plurality of clock signals for operation. The digital baseband processor also includes a power management circuit which may power down the system oscillator when modules such as the digital signal processor and microcontroller do not require clock signals derived from the system oscillator. The power management circuit may gate off clock signals to modules when those modules do not require clock signals, without powering down the system oscillator.

Abstract: A high-speed programmable serial port having a finite state machine, a clock generator capable of controlling shifting of bits from a shift register and a shift register having a bit counter capable of maintaining a numbered count of data bits in a serial output. The clock generator and shift register reduce the burdens on a finite state machine, thus improving data throughput and the ability to provided data according to a multitude of data protocols.

Abstract: Methods and apparatus for accessing flash memory in a continued burst mode are provided. The apparatus includes a processor for executing instructions including memory access instructions, the processor generating a next access signal that indicates if a next memory access is in sequence with a current memory access, a memory having a continued burst mode of operation, and a bus interface for controlling access to the memory in response to the memory access instructions. The bus interface unit enables the continued burst mode of the memory while the next access signal is asserted.

Abstract: Methods and apparatus are provided for operating an embedded processor system that includes a processor and a cache memory. The method includes filling one or more lines in the cache memory with data associated with a first task, executing the first task, and, in response to a cache miss during execution of the first task, performing a cache line fill operation and, during the cache line fill operation, executing a second task. The cache memory may notify the processor of the line fill operation by generating a processor interrupt or by notifying a task scheduler running on the processor.

Abstract: A clock enable system for a multichip device includes a first integrated circuit including a clock signal and at least a second integrated circuit including at least one functional block periodically requiring clock signals from the first integrated circuit; a clock required circuit responsive to each functional block for providing a clock required signal in response to activation of any one or more of the functional blocks; and a clock enable circuit responsive to the clock required signal for enabling the first integrated circuit to provide clock signals to the functional blocks on the second integrated circuit.

Abstract: A multiple bus architecture includes multiple processors, and one or more shared peripherals such as memory. The architecture includes plural bus masters, each connected to its own bus. There are also plural bus slaves, each connected to its own bus. A bus arbitration module selectively interconnects the buses, so that when the plural bus masters each access a different bus slave, no blocking occurs, and when the plural bus masers each access a same bus slave, bandwidth starvation is avoided. The architecture is supported by a bus arbitration method including hierarchical application of an interrupt-based method, an assigned slot rotation method and a round-robin method, which avoids both bandwidth starvation and lockout during extended periods of bus contention.

Abstract: A dynamic power controller is provided that identifies a clock frequency requirement of a processor and determines a voltage requirement to support the clock frequency requirement. The dynamic power controller transitions the processor to a power state defined by the clock frequency requirement and the voltage requirement. In particular, a voltage level indicated by the voltage requirement is supplied to the processor and the frequency distribution indicated by the frequency requirement is provided to the clocks signals of the processor.

Abstract: The present invention is directed to methods and apparatus which may be used to help prevent electronic devices such as, for example, cell phones from operating with software copied from (and only authorized for use by) another device. The present invention is also directed to devices such as, for example, cell phones, that employ any of such methods and apparatus.