Patents by Inventor Joey Cai

Joey Cai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12342448
    Abstract: A circuit board includes chip die mounted on a three dimensional rectangular structure, a three dimensional triangular prism structure, or a combination thereof. A ball grid array for the chip die mounted on any such three dimensional structure is interposed between the three dimensional structure and the circuit board itself.
    Type: Grant
    Filed: April 18, 2022
    Date of Patent: June 24, 2025
    Assignee: NVIDIA Corp.
    Inventors: Joey Cai, Tiger Yan, Zhu Hao, Yi Dinghai
  • Publication number: 20250048532
    Abstract: A circuit board includes chip die mounted on a three dimensional rectangular structure, a three dimensional triangular prism structure, or a combination thereof. A ball grid array for the chip die mounted on any such three dimensional structure is interposed between the three dimensional structure and the circuit board itself.
    Type: Application
    Filed: October 18, 2024
    Publication date: February 6, 2025
    Applicant: NVIDIA Corp.
    Inventors: Joey Cai, Tiger Yan, Zhu Hao, Yi Dinghai
  • Publication number: 20240332223
    Abstract: An integrated circuit die substrate has one or more capacitors attached to an edge surface of the substrate. The substrate has a top surface and a bottom surface, at least one of which includes a die mounting area, and at least one of which includes system interconnect terminals. A substrate edge surface is disposed along a peripheral end of the substrate and is oriented substantially orthogonally to the top and bottom surfaces. A pair of conductive edge terminals is disposed on the substrate edge surface. Each of the edge terminals is electrically coupled to a respective substrate conductor disposed on or inside the substrate. A capacitor is attached exteriorly to the substrate at the substrate edge surface such that terminals of the capacitor are electrically coupled to respective ones of the edge terminals. An integrated circuit die is attached at the die mounting area.
    Type: Application
    Filed: March 5, 2024
    Publication date: October 3, 2024
    Applicant: NVIDIA Corporation
    Inventors: Tracy Fu, Tiger Yan, Joey Cai, Zach Wang
  • Publication number: 20230337350
    Abstract: A circuit board includes chip die mounted on a three dimensional rectangular structure, a three dimensional triangular prism structure, or a combination thereof. A ball grid array for the chip die mounted on any such three dimensional structure is interposed between the three dimensional structure and the circuit board itself.
    Type: Application
    Filed: April 18, 2022
    Publication date: October 19, 2023
    Applicant: NVIDIA Corp.
    Inventors: Joey Cai, Tiger Yan, Zhu Hao, Yi Dinghai
  • Patent number: 11791319
    Abstract: Edge-connected semiconductor systems are described along with methods of making and using the same. First and second integrated circuit packages are obtained, each including a substrate assembly having top and bottom sides and an edge that extends between the top and the bottom sides. Edge contacts are disposed on the edges of the substrate assemblies. A ganged assembly is formed by establishing conductive paths between the edge contacts of the substrate assemblies. The ganged assembly is coupled to a printed circuit board (“PCB”) by coupling host contacts on one or more of the substrate assemblies to corresponding contacts on the PCB.
    Type: Grant
    Filed: February 1, 2021
    Date of Patent: October 17, 2023
    Assignee: NVIDIA Corporation
    Inventors: Joey Cai, Tiger Yan, Jacky Zhu, Oliver Yi, Zach Wang
  • Patent number: 11646240
    Abstract: Through-hole mounted semiconductor assemblies are described. A printed circuit board (“PCB”) has first and second PCB sides and has a through hole therein. The through hole defines a hole area. A semiconductor package may be disposed in the hole area such that the semiconductor package is at least partially exposed on one or more of the first and the second PCB sides. Package contacts on the semiconductor package may be electrically coupled to PCB contacts disposed on one or more of the PCB sides. In some embodiments, one or more support structures may be coupled to the PCB and may touch the semiconductor package. In some embodiments, cooling devices may be placed in thermal communication with the semiconductor package on both sides of the PCB.
    Type: Grant
    Filed: February 3, 2021
    Date of Patent: May 9, 2023
    Assignee: NVIDIA Corporation
    Inventors: Joey Cai, Tiger Yan, Jacky Zhu, Oliver Yi
  • Publication number: 20220246487
    Abstract: Through-hole mounted semiconductor assemblies are described. A printed circuit board (“PCB”) has first and second PCB sides and has a through hole therein. The through hole defines a hole area. A semiconductor package may be disposed in the hole area such that the semiconductor package is at least partially exposed on one or more of the first and the second PCB sides. Package contacts on the semiconductor package may be electrically coupled to PCB contacts disposed on one or more of the PCB sides. In some embodiments, one or more support structures may be coupled to the PCB and may touch the semiconductor package. In some embodiments, cooling devices may be placed in thermal communication with the semiconductor package on both sides of the PCB.
    Type: Application
    Filed: February 3, 2021
    Publication date: August 4, 2022
    Inventors: Joey Cai, Tiger Yan, Jacky Zhu, Oliver Yi
  • Publication number: 20220246589
    Abstract: Edge-connected semiconductor systems are described along with methods of making and using the same. First and second integrated circuit packages are obtained, each including a substrate assembly having top and bottom sides and an edge that extends between the top and the bottom sides. Edge contacts are disposed on the edges of the substrate assemblies. A ganged assembly is formed by establishing conductive paths between the edge contacts of the substrate assemblies. The ganged assembly is coupled to a printed circuit board (“PCB”) by coupling host contacts on one or more of the substrate assemblies to corresponding contacts on the PCB.
    Type: Application
    Filed: February 1, 2021
    Publication date: August 4, 2022
    Inventors: Joey Cai, Tiger Yan, Jacky Zhu, Oliver Yi, Zach Wang
  • Publication number: 20200363859
    Abstract: Scalable displaying for a mobile device is provided, including receiving an instruction to scale a display of the mobile device, and scaling the display on a screen of the mobile device in response to the instruction. The scalable displaying for the mobile device can be provided by activating only a portion of the screen of the mobile device for use as a display, such that an overall power consumed by the screen is reduced.
    Type: Application
    Filed: June 25, 2019
    Publication date: November 19, 2020
    Inventors: Oliver Yi, Tiger Yan, Jacky Zhu, Joey Cai
  • Patent number: 10757812
    Abstract: The present invention provides a printed circuit board and a layout method thereof and an electronic equipment. On the printed circuit board is arranged a first processor chip and a second processor chip, wherein the first processor chip is arranged on a first surface of the printed circuit board; the second processor chip is arranged on a second surface of the printed circuit board; and a first through-hole is disposed on the printed circuit board, part of pins of the first processor chip being connected to part of pins of the second processor chip via the first through-hole.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: August 25, 2020
    Assignee: NVIDIA CORPORATION
    Inventors: Joey Cai, Tiger Yan, Oliver Yi, Jacky Zhu, Roman Li