Patents by Inventor Joey M. Poss

Joey M. Poss has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11961542
    Abstract: Various illustrative aspects are directed to a data storage device comprising a slider with a resistive temperature detector with a first resistance, a resistance detection circuit electrically coupled to the first resistance and comprising a low and high frequency path corresponding to a DC and AC mode, respectively, and one or more processing devices configured to: bias the first resistance with a voltage bias, where the first resistance is coupled to a first and second amplifier, control a pulse generator to add a bias pulse on the HF path to generate a HF resistance detection signal, where the second amplifier is biased using the voltage bias and the bias pulse, control a clock to chop a LF signal at the first amplifier on the LF path, demodulate the chopped LF signal to generate a LF resistance detection signal, and concurrently process the HF and LF resistance detection signals.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: April 16, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: John Contreras, Joey M. Poss, Ronald Chang, Bernhard E. Knigge
  • Publication number: 20240105217
    Abstract: Various illustrative aspects are directed to a data storage device comprising a storage medium and a head configured to access the storage medium. The head comprises a first write assist element and a second write assist element. Control circuitry for driving the head is configured to apply a first write assist current Im that is synchronized to a write data current Iw to the first write assist element; and to apply a second DC write assist current Imdc to the second write assist element.
    Type: Application
    Filed: September 14, 2023
    Publication date: March 28, 2024
    Inventors: Joey M. Poss, Yunfei Ding, John T. Contreras
  • Patent number: 11874182
    Abstract: Various illustrative aspects are directed to a data storage device comprising a slider with a resistive temperature detector (RTD) having a first resistance electrically connected to a first amplifier and a plurality of controlled current sources and switches, and one or more processing devices configured to: control the switches to generate an alternating-bias signal having a first clock frequency for biasing the first resistance, modulate an input signal of the first amplifier using the first clock frequency to generate a modulated signal, demodulate an amplified modulated signal at an output of a second amplifier using the first clock frequency to generate a resistance detection signal, the second amplifier coupled to the first amplifier, and process the resistance detection signal to determine the first resistance and/or a change in value of the first resistance.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: January 16, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: John Contreras, Joey M. Poss, Ronald Chang, Bernhard E. Knigge
  • Publication number: 20240005957
    Abstract: Various illustrative aspects are directed to a data storage device comprising a slider with a resistive temperature detector with a first resistance, a resistance detection circuit electrically coupled to the first resistance and comprising a low and high frequency path corresponding to a DC and AC mode, respectively, and one or more processing devices configured to: bias the first resistance with a voltage bias, where the first resistance is coupled to a first and second amplifier, control a pulse generator to add a bias pulse on the HF path to generate a HF resistance detection signal, where the second amplifier is biased using the voltage bias and the bias pulse, control a clock to chop a LF signal at the first amplifier on the LF path, demodulate the chopped LF signal to generate a LF resistance detection signal, and concurrently process the HF and LF resistance detection signals.
    Type: Application
    Filed: August 9, 2022
    Publication date: January 4, 2024
    Inventors: John Contreras, Joey M. Poss, Ronald Chang, Bernhard E. Knigge
  • Publication number: 20240003750
    Abstract: Various illustrative aspects are directed to a data storage device comprising a slider with a resistive temperature detector (RTD) having a first resistance electrically connected to a first amplifier and a plurality of controlled current sources and switches, and one or more processing devices configured to: control the switches to generate an alternating-bias signal having a first clock frequency for biasing the first resistance, modulate an input signal of the first amplifier using the first clock frequency to generate a modulated signal, demodulate an amplified modulated signal at an output of a second amplifier using the first clock frequency to generate a resistance detection signal, the second amplifier coupled to the first amplifier, and process the resistance detection signal to determine the first resistance and/or a change in value of the first resistance.
    Type: Application
    Filed: August 9, 2022
    Publication date: January 4, 2024
    Inventors: John Contreras, Joey M. Poss, Ronald Chang, Bernhard E. Knigge
  • Publication number: 20230298621
    Abstract: A data storage device is disclosed comprising a head actuated over an energy assisted magnetic media comprising a plurality of data tracks, wherein each data track comprises a plurality of data sectors. A write operation to a first data sector is executed by applying a first current to a write coil of the head while the head is over a second data sector preceding the first data sector, wherein the first current comprises a first amplitude. A second current is applied to the write coil while the head is over the first data sector, wherein the second current comprises a second amplitude lower than the first amplitude.
    Type: Application
    Filed: May 23, 2023
    Publication date: September 21, 2023
    Applicant: Western Digital Technologies, Inc.
    Inventors: Joey M. POSS, Naoto ITO, Phillip S. HARALSON
  • Patent number: 11735210
    Abstract: Example preamplifier circuits, data storage devices, and methods to provide a preamplifier circuit with separate read and write power channels are described. The preamplifier circuit may include a write driver circuit configured to send a write signal to a writer element of a data storage device and a read driver circuit configured to receive a read signal from a reader element of the data storage device. The write driver circuit may receive a write power signal through a write power channel of a bus interface and the read driver circuit may receive a read power signal through a read power channel of the bus interface, where the write power signal and the read power signal are different. In some configurations, the different read and write power signals may be received from a switching regulator on the printed circuit board that mounts other data storage device electronics, such as the drive controller circuit and/or read/write channel circuit.
    Type: Grant
    Filed: December 21, 2021
    Date of Patent: August 22, 2023
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Joey M. Poss, Erhard Schreck
  • Patent number: 11694712
    Abstract: A data storage device is disclosed comprising a head actuated over an energy assisted magnetic media comprising a plurality of data tracks, wherein each data track comprises a plurality of data sectors. A write operation to a first data sector is executed by applying a first current to a write coil of the head while the head is over a second data sector preceding the first data sector, wherein the first current comprises a first amplitude. A second current is applied to the write coil while the head is over the first data sector, wherein the second current comprises a second amplitude lower than the first amplitude.
    Type: Grant
    Filed: April 27, 2021
    Date of Patent: July 4, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Joey M. Poss, Naoto Ito, Phillip S. Haralson
  • Publication number: 20230197108
    Abstract: Example preamplifier circuits, data storage devices, and methods to provide a preamplifier circuit with separate read and write power channels are described. The preamplifier circuit may include a write driver circuit configured to send a write signal to a writer element of a data storage device and a read driver circuit configured to receive a read signal from a reader element of the data storage device. The write driver circuit may receive a write power signal through a write power channel of a bus interface and the read driver circuit may receive a read power signal through a read power channel of the bus interface, where the write power signal and the read power signal are different. In some configurations, the different read and write power signals may be received from a switching regulator on the printed circuit board that mounts other data storage device electronics, such as the drive controller circuit and/or read/write channel circuit.
    Type: Application
    Filed: December 21, 2021
    Publication date: June 22, 2023
    Inventors: Joey M. Poss, Erhard Schreck
  • Patent number: 11615804
    Abstract: A data storage device is disclosed comprising a storage medium and a head configured to access the storage medium, wherein the head comprises a first write assist element (WA1) comprising a first terminal and a second terminal and a second write assist element (WA2) comprising a first terminal and a second terminal. The second terminal of the WA1 and the second terminal of the WA2 are coupled together to form a common node. A first bias signal is applied to the first terminal of the WA1, a second bias signal is applied to the first terminal of the WA2, and a common mode voltage is applied to the common node.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: March 28, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Joey M. Poss, John T. Contreras, Ian Robson McFadyen, Yaw Shing Tang
  • Publication number: 20220343943
    Abstract: A data storage device is disclosed comprising a head actuated over an energy assisted magnetic media comprising a plurality of data tracks, wherein each data track comprises a plurality of data sectors. A write operation to a first data sector is executed by applying a first current to a write coil of the head while the head is over a second data sector preceding the first data sector, wherein the first current comprises a first amplitude. A second current is applied to the write coil while the head is over the first data sector, wherein the second current comprises a second amplitude lower than the first amplitude.
    Type: Application
    Filed: April 27, 2021
    Publication date: October 27, 2022
    Inventors: JOEY M. POSS, NAOTO ITO, PHILLIP S. HARALSON
  • Patent number: 11482247
    Abstract: A data storage device is disclosed comprising a head actuated over a magnetic media comprising a plurality of tracks. A first pattern of magnetic transitions is written to a first segment of a first track. Preparation is made to write a second pattern of magnetic transitions to a second segment of a second track adjacent the first segment of the first track. When the second pattern matches the first pattern, a write boost is configured to a first setting, and when the second pattern does not match the first pattern, the write boost is configured to a second setting. The second pattern of magnetic transitions is then written to the second segment of the second track using the configured write boost.
    Type: Grant
    Filed: February 23, 2021
    Date of Patent: October 25, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Guoxiao Guo, Charles A. Park, David Scott C. Amiss, Duc H. Banh, Joey M. Poss, Weldon M. Hanson
  • Publication number: 20220246173
    Abstract: A data storage device is disclosed comprising a head actuated over a magnetic media comprising a plurality of tracks. A first pattern of magnetic transitions is written to a first segment of a first track. Preparation is made to write a second pattern of magnetic transitions to a second segment of a second track adjacent the first segment of the first track. When the second pattern matches the first pattern, a write boost is configured to a first setting, and when the second pattern does not match the first pattern, the write boost is configured to a second setting. The second pattern of magnetic transitions is then written to the second segment of the second track using the configured write boost.
    Type: Application
    Filed: February 23, 2021
    Publication date: August 4, 2022
    Inventors: Guoxiao Guo, Charles A. Park, David Scott C. Amiss, Duc H. Banh, Joey M. Poss, Weldon M. Hanson
  • Patent number: 11404079
    Abstract: A data storage device is disclosed comprising a head actuated over a magnetic media. A write operation is executed to a first data sector by writing to at least part of a defective data sector preceding the first data sector in order to achieve a target fly height of the head prior to writing to the first data sector.
    Type: Grant
    Filed: April 27, 2021
    Date of Patent: August 2, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Joey M. Poss, Naoto Ito, Phillip S. Haralson
  • Patent number: 11361786
    Abstract: A data storage device is disclosed comprising a head actuated over a magnetic media, wherein the head comprises a read element configured to generate a read signal when reading data from the magnetic media. A common-source common-gate (CS-CG) differential amplifier is coupled to the read element through a transmission line having a transmission line impedance Z0. A feedback circuit is coupled between an output of the CS-CG differential amplifier and an input of the CS-CG differential amplifier, wherein the feedback circuit is configured so that an input impedance of the CS-CG differential amplifier substantially matches the transmission line impedance Z0.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: June 14, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: John T. Contreras, Joey M. Poss
  • Publication number: 20220165299
    Abstract: A data storage device is disclosed comprising a head actuated over a magnetic media, wherein the head comprises a read element configured to generate a read signal when reading data from the magnetic media. A common-source common-gate (CS-CG) differential amplifier is coupled to the read element through a transmission line having a transmission line impedance Z0. A feedback circuit is coupled between an output of the CS-CG differential amplifier and an input of the CS-CG differential amplifier, wherein the feedback circuit is configured so that an input impedance of the CS-CG differential amplifier substantially matches the transmission line impedance Z0.
    Type: Application
    Filed: February 22, 2021
    Publication date: May 26, 2022
    Inventors: John T. Contreras, Joey M. Poss
  • Patent number: 11295764
    Abstract: A data storage device is disclosed comprising a head actuated over a magnetic media, wherein the head comprises a write element and a first read element. A preamp circuit comprising an interface includes at least a write line associated with the write element of the head and a first read line associated with the first read element of the head. A first read signal is received from the preamp circuit over the first read line during a read operation, and configuration data is transmitted to the preamp circuit over the first read line during a write operation.
    Type: Grant
    Filed: March 28, 2021
    Date of Patent: April 5, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Jonas A. Goode, Richard L. Galbraith, Joey M. Poss, John T. Contreras
  • Patent number: 11200912
    Abstract: A data storage device is disclosed comprising a head actuated over a magnetic media. A write boost is configured to a first setting, and a first pattern of magnetic transitions is written to a first servo field of a servo sector on the magnetic media using the first setting for the write boost. The write boost is configured to a second setting different from the first setting, and the first pattern of magnetic transitions is written to a second servo field of the servo sector on the magnetic media using the second setting for the write boost.
    Type: Grant
    Filed: February 23, 2021
    Date of Patent: December 14, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Guoxiao Guo, Charles A. Park, David Scott C. Amiss, Duc H. Banh, Joey M. Poss, Weldon M. Hanson
  • Patent number: 10825474
    Abstract: A data storage device is disclosed comprising a first head actuated over a first disk surface, the first head comprising a plurality of elements including a first element. During a first write operation of the first head, a first bias signal having a first polarity is applied to the first element, and a write interval of the first write operation is measured. During a non-write mode of the first head, a second bias signal having a second polarity opposite the first polarity is applied to the first element during a reverse bias interval that is based on the write interval of the first write operation.
    Type: Grant
    Filed: January 30, 2020
    Date of Patent: November 3, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Joey M. Poss, Ian Robson McFadyen, Jih-shiuan Luo, Yunfei Ding
  • Publication number: 20200168247
    Abstract: A data storage device is disclosed comprising a first head actuated over a first disk surface, the first head comprising a plurality of elements including a first element. During a first write operation of the first head, a first bias signal having a first polarity is applied to the first element, and a write interval of the first write operation is measured. During a non-write mode of the first head, a second bias signal having a second polarity opposite the first polarity is applied to the first element during a reverse bias interval that is based on the write interval of the first write operation.
    Type: Application
    Filed: January 30, 2020
    Publication date: May 28, 2020
    Inventors: Joey M. POSS, Ian Robson MCFADYEN, Jih-shiuan LUO, Yunfei DING