Patents by Inventor Joff Derluyn
Joff Derluyn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11287249Abstract: A system for in-situ measurement of a curvature of a surface of a wafer comprises: a multiwavelength light source module, adapted to emit incident light comprising a plurality of wavelengths; an optical setup configured to combine the incident light into a single beam and to guide the single beam towards a surface of a wafer such that the single beam hits the surface at a single measuring spot on the surface; and a curvature determining unit, configured to determine a curvature of the surface of the wafer from reflected light corresponding to the single beam being reflected on the surface at the single measuring spot.Type: GrantFiled: December 20, 2018Date of Patent: March 29, 2022Assignee: SOITEC BELGIUMInventors: Roland Pusche, Stefan Degroote, Joff Derluyn
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Publication number: 20210336042Abstract: A high electron mobility transistor for analog applications comprising: a substrate; an epitaxial III-N semiconductor layer stack on top of said substrate, said epitaxial III-N semiconductor layer stack comprising: a first active III-N layer; and a second active III-N layer comprising a recess; with a two dimensional Electron Gas in between III-N; a gate on top of said epitaxial III-N semiconductor layer stack; and a passivation stack between said epitaxial III-N semiconductor layer stack and said gate, wherein said passivation stack comprises an electron accepting dielectric layer adapted to deplete said two dimensional Electron Gas when said gate is not biased; wherein said electron accepting dielectric layer extends in said recess and comprises magnesium nitride doped with silicon and/or aluminum.Type: ApplicationFiled: July 8, 2021Publication date: October 28, 2021Inventor: Joff DERLUYN
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Patent number: 11094812Abstract: A high electron mobility transistor for analog applications comprising: a substrate; an epitaxial III-N semiconductor layer stack on top of said substrate, said epitaxial III-N semiconductor layer stack comprising: a first active III-N layer; and a second active III-N layer comprising a recess; with a two dimensional Electron Gas in between III-N; a gate on top of said epitaxial III-N semiconductor layer stack; and a passivation stack between said epitaxial III-N semiconductor layer stack and said gate, wherein said passivation stack comprises an electron accepting dielectric layer adapted to deplete said two dimensional Electron Gas when said gate is not biased; wherein said electron accepting dielectric layer extends in said recess and comprises magnesium nitride doped with silicon and/or aluminum.Type: GrantFiled: June 19, 2018Date of Patent: August 17, 2021Assignee: Soitec BelgiumInventor: Joff Derluyn
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Publication number: 20200393241Abstract: A system for in-situ measurement of a curvature of a surface of a wafer comprises: a multiwavelength light source module, adapted to emit incident light comprising a plurality of wavelengths; an optical setup configured to combine the incident light into a single beam and to guide the single beam towards a surface of a wafer such that the single beam hits the surface at a single measuring spot on the surface; and a curvature determining unit, configured to determine a curvature of the surface of the wafer from reflected light corresponding to the single beam being reflected on the surface at the single measuring spot.Type: ApplicationFiled: December 20, 2018Publication date: December 17, 2020Inventors: Roland PUSCHE, Stefan DEGROOTE, Joff DERLUYN
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Publication number: 20200332438Abstract: A method for forming silicon carbide onto a silicon substrate by reaction of said silicon substrate and a first precursor comprising indium and a plurality of carbon atoms.Type: ApplicationFiled: December 20, 2018Publication date: October 22, 2020Inventors: Roland PUSCHE, Stefan DEGROOTE, Joff DERLUYN
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Publication number: 20200176593Abstract: A high electron mobility transistor for analog applications comprising: a substrate; an epitaxial III-N semiconductor layer stack on top of said substrate, said epitaxial III-N semiconductor layer stack comprising: a first active III-N layer; and a second active III-N layer comprising a recess; with a two dimensional Electron Gas in between III-N; a gate on top of said epitaxial III-N semiconductor layer stack; and a passivation stack between said epitaxial III-N semiconductor layer stack and said gate, wherein said passivation stack comprises an electron accepting dielectric layer adapted to deplete said two dimensional Electron Gas when said gate is not biased; wherein said electron accepting dielectric layer extends in said recess and comprises magnesium nitride doped with silicon and/or aluminum.Type: ApplicationFiled: June 19, 2018Publication date: June 4, 2020Inventor: Joff DERLUYN
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Patent number: 9991346Abstract: A semiconductor structure includes a buffer layer stack comprising a plurality of III-V material layers, and the buffer layer stack includes at least one layered substructure. Each layered substructure comprises a compressive stress inducing structure between a respective first buffer layer and a respective second buffer layer positioned higher in the buffer layer stack than the respective first buffer layer. A lower surface of the respective second buffer layer has a lower Al content than an upper surface of the respective first buffer layer. An active semiconductor layer of the III-V type is provided on the buffer layer stack. The surface of the respective relaxation layers is sufficiently rough to inhibit the relaxation of the respective second buffer layer, and comprises a Root Mean Square (RMS) roughness larger than 1 nm. A method is provided for producing the semiconductor structure.Type: GrantFiled: July 22, 2015Date of Patent: June 5, 2018Assignee: EPIGAN NVInventors: Joff Derluyn, Stefan Degroote
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Patent number: 9847412Abstract: A device comprising a III-N layer stack featuring a two-dimensional electron gas is disclosed, comprising: —a III-N layer; —a AI-III-N layer on top of the III-N layer; —a passivation layer on top of said AI-III-N layer, the passivation layer comprising Silicon Nitride (SiN); wherein said passivation layer comprises a fully crystalline sub layer at the AI-III-N interface and at least part of the fully crystalline sub layer comprises Al and/or B; and associated methods for manufacturing the device.Type: GrantFiled: October 12, 2012Date of Patent: December 19, 2017Assignee: EpiGaN nvInventors: Joff Derluyn, Stefan Degroote, Marianne Germain
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Patent number: 9748331Abstract: Disclosed are methods of growing III-V epitaxial layers on a substrate, semiconductor structures thus obtained, and devices comprising such semiconductor structures. An example semiconductor substrate includes a substrate and a buffer layer on top of the substrate, where a conductive path is present between the substrate and buffer layer. A conductive path may be present in the conductive interface, and the conductive path may be interrupted by one or more local electrical isolations. The local electrical isolation(s) may be positioned with the device such that at least one of the local electrical isolation(s) is located between a high voltage terminal and a low voltage terminal of the device.Type: GrantFiled: December 10, 2015Date of Patent: August 29, 2017Assignee: EpiGaN NVInventors: Joff Derluyn, Stefan Degroote, Marianne Germain
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Publication number: 20170229549Abstract: A semiconductor structure includes a buffer layer stack comprising a plurality of III-V material layers, and the buffer layer stack includes at least one layered substructure. Each layered substructure comprises a compressive stress inducing structure between a respective first buffer layer and a respective second buffer layer positioned higher in the buffer layer stack than the respective first buffer layer. A lower surface of the respective second buffer layer has a lower Al content than an upper surface of the respective first buffer layer. An active semiconductor layer of the III-V type is provided on the buffer layer stack. The surface of the respective relaxation layers is sufficiently rough to inhibit the relaxation of the respective second buffer layer, and comprises a Root Mean Square (RMS) roughness larger than 1 nm. A method is provided for producing the semiconductor structure.Type: ApplicationFiled: July 22, 2015Publication date: August 10, 2017Inventors: Joff DERLUYN, Stefan DEGROOTE
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Patent number: 9543424Abstract: Disclosed are methods of growing III-V epitaxial layers on a substrate, a semiconductor structure comprising a substrate, a device comprising such a semiconductor structure, and an electronic circuit. Group III-nitride devices, such as, for example, high-electron-mobility transistors, may include a two-dimensional electron gas (2DEG) between two active layers. For example, the 2DEG may be between a GaN layer and a AlGaN layer. These transistors may work in depletion-mode operation, which means the channel has to be depleted to turn the transistor off. For certain applications, such as, for example, power switching or integrated logic, negative polarity gate supply is undesired. Transistors may then work in enhancement mode (E-mode).Type: GrantFiled: July 6, 2012Date of Patent: January 10, 2017Assignee: EpiGaN NVInventors: Joff Derluyn, Stefan Degroote, Marianne Germain
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Publication number: 20160099309Abstract: Disclosed are methods of growing III-V epitaxial layers on a substrate, semiconductor structures thus obtained, and devices comprising such semiconductor structures. An example semiconductor substrate includes a substrate and a buffer layer on top of the substrate, where a conductive path is present between the substrate and buffer layer. A conductive path may be present in the conductive interface, and the conductive path may be interrupted by one or more local electrical isolations. The local electrical isolation(s) may be positioned with the device such that at least one of the local electrical isolation(s) is located between a high voltage terminal and a low voltage terminal of the device.Type: ApplicationFiled: December 10, 2015Publication date: April 7, 2016Applicant: EpiGaN NVInventors: Joff Derluyn, Stefan Degroote, Marianne Germain
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Patent number: 9230803Abstract: Disclosed are methods of growing III-V epitaxial layers on a substrate, semiconductor structures thus obtained, and devices comprising such semiconductor structures. An example semiconductor substrate includes a substrate and a buffer layer on top of the substrate, where a conductive path is present between the substrate and buffer layer. A conductive path may be present in the conductive interface, and the conductive path may be interrupted by one or more local electrical isolations. The local electrical isolation(s) may be positioned with the device such that at least one of the local electrical isolation(s) is located between a high voltage terminal and a low voltage terminal of the device.Type: GrantFiled: July 6, 2012Date of Patent: January 5, 2016Assignee: Epigan NVInventors: Joff Derluyn, Stefan Degroote, Marianne Germain
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Publication number: 20150008444Abstract: A device comprising a III-N layer stack featuring a two-dimensional electron gas is disclosed, comprising: a III-N layer; a AI-III-N layer on top of the III-N layer; a passivation layer on top of said AI-III-N layer, the passivation layer comprising Silicon Nitride (SiN); wherein said passivation layer comprises a fully crystalline sub layer at the AI-III-N interface and at least part of the fully crystalline sub layer comprises Al and/or B; and associated methods for manufacturing the device.Type: ApplicationFiled: October 12, 2012Publication date: January 8, 2015Applicant: EPIGAN NVInventors: Joff Derluyn, Stefan Degroote, Marianne Germain
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Patent number: 8809138Abstract: A semiconductor device is disclosed. In one aspect, the device has a first and second active layer on a substrate, the second active layer having a higher bandgap than the first active layer, being substantially Ga-free and including at least Al. The device has a gate insulating layer on a part of the second active layer formed by thermal oxidation of a part of the second active layer. The device has a gate electrode on at least a part of the gate insulating layer and a source electrode and drain electrode on the second active layer. The device has, when in operation and when the gate and source electrode are at the same voltage, a two-dimensional electron gas layer between the first and second active layer only outside the location of the gate electrode and not at the location of the gate electrode.Type: GrantFiled: October 12, 2012Date of Patent: August 19, 2014Assignee: IMECInventors: Joff Derluyn, Farid Medjdoub, Marianne Germain
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Publication number: 20140167114Abstract: Disclosed are methods of growing III-V epitaxial layers on a substrate, semiconductor structures thus obtained, and devices comprising such semiconductor structures. An example semiconductor substrate includes a substrate and a buffer layer on top of the substrate, where a conductive path is present between the substrate and buffer layer. A conductive path may be present in the conductive interface, and the conductive path may be interrupted by one or more local electrical isolations. The local electrical isolation(s) may be positioned with the device such that at least one of the local electrical isolation(s) is located between a high voltage terminal and a low voltage terminal of the device.Type: ApplicationFiled: July 6, 2012Publication date: June 19, 2014Applicant: EpiGaN NVInventors: Joff Derluyn, Stefan Degroote, Marianne Germain
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Publication number: 20140159119Abstract: Disclosed are methods of growing III-V epitaxial layers on a substrate, a semiconductor structure comprising a substrate, a device comprising such a semiconductor structure, and an electronic circuit. Group III-nitride devices, such as, for example, high-electron-mobility transistors, may include a two-dimensional electron gas (2DEG) between two active layers. For example, the 2DEG may be between a GaN layer and a AlGaN layer. These transistors may work in depletion-mode operation, which means the channel has to be depleted to turn the transistor off. For certain applications, such as, for example, power switching or integrated logic, negative polarity gate supply is undesired. Transistors may then work in enhancement mode (E-mode).Type: ApplicationFiled: July 6, 2012Publication date: June 12, 2014Applicant: EpiGaN NVInventors: Joff Derluyn, Stefan Degroote, Marianne Germain
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Publication number: 20130237021Abstract: A method is disclosed for producing Group III-N field-effect devices, such as HEMT, MOSHFET, MISHFET or MESFET devices, comprising two active layers, e.g. a GaN/AlGaN layer. The method produces an enhancement mode device of this type, i.e. a normally-off device, by providing a passivation layer on the AlGaN layer, etching a hole in the passivation layer and not in the layers underlying the passivation layer, and depositing the gate contact in the hole, while the source and drain are deposited directly on the passivation layer. The characteristics of the active layers and/or of the gate are chosen such that no two-dimensional electron gas layer is present underneath the gate, when a zero voltage is applied to the gate. A device with this behavior is also disclosed.Type: ApplicationFiled: February 27, 2013Publication date: September 12, 2013Applicants: Katholieke Universiteit Leuven, IMECInventors: Joff Derluyn, Steven Boeykens, Marianne Germain, Gustaaf Borghs
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Patent number: 8492261Abstract: A method for manufacturing a III-V CMOS device is disclosed. The device includes a first and second main contact and a control contact. In one aspect, the method includes providing the control contact by using damascene processing. The method thus allows obtaining a control contact with a length of between about 20 nm and 5 ?m and with good Schottky behavior. Using low-resistive materials such as Cu allows reducing the gate resistance thus improving the high-frequency performance of the III-V CMOS device.Type: GrantFiled: January 19, 2010Date of Patent: July 23, 2013Assignee: IMECInventors: Marleen Van Hove, Joff Derluyn
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Patent number: 8399911Abstract: A method is disclosed for producing Group III-N field-effect devices, such as HEMT, MOSHFET, MISHFET or MESFET devices, comprising two active layers, e.g. a GaN/AlGaN layer. The method produces an enhancement mode device of this type, i.e. a normally-off device, by providing a passivation layer on the AlGaN layer, etching a hole in the passivation layer and not in the layers underlying the passivation layer, and depositing the gate contact in the hole, while the source and drain are deposited directly on the passivation layer. The characteristics of the active layers and/or of the gate are chosen such that no two-dimensional electron gas layer is present underneath the gate, when a zero voltage is applied to the gate. A device with this behavior is also disclosed.Type: GrantFiled: June 6, 2007Date of Patent: March 19, 2013Assignee: IMECInventors: Joff Derluyn, Steven Boeykens, Marianne Germain, Gustaaf Borghs