Abstract: An RF power device comprising a power transistor fabricated in a first semiconductor chip and a MOSCAP type structure fabricated in a second semiconductor chip. A voltage limiting device is provided for protecting the power transistor from input voltage spikes and is preferably fabricated in the semiconductor chip along with the MOSCAP. Alternatively, the voltage limiting device can be a discrete element fabricated on or adjacent to the capacitor semiconductor chip. By removing the voltage limiting device from the power transistor chip, fabrication and testing of the voltage limiting device is enhanced, and semiconductor area for the power device is increased and aids in flexibility of device fabrication.

Abstract: An RF power device comprising a power transistor fabricated in a first semiconductor chip and a MOSCAP type structure fabricated in a second semiconductor chip. A voltage limiting device is provided for protecting the power transistor from input voltage spikes and is preferably fabricated in the semiconductor chip along with the MOSCAP. Alternatively, the voltage limiting device can be a discrete element fabricated on or adjacent to the capacitor semiconductor chip. By removing the voltage limiting device from the power transistor chip, fabrication and testing of the voltage limiting device is enhanced, and semiconductor area for the power device is increased and aids in flexibility of device fabrication.

Abstract: A BiCMOS manufacturing process for fabricating an emitter of a bipolar transistor includes the steps of forming footings on a silicon substrate for prospectively bearing edges of the emitter, forming a polysilicon emitter having a medial portion overlying the silicon substrate and lateral edges on the footings, removing the footings leaving notches at the lateral edges of the polysilicon emitter and refilling the notches with a thin polysilicon film. The bipolar transistor in a BiCMOS integrated circuit resulting from this process includes a silicon semiconductor substrate having a substantially flat surface, a field oxide film laterally bounding the silicon semiconductor substrate and a polysilicon emitter abutting the flat surface of the silicon semiconductor substrate.

Abstract: A BiCMOS manufacturing process for fabricating an emitter of a bipolar transistor includes the steps of forming footings on a silicon substrate for prospectively bearing edges of the emitter, forming a polysilicon emitter having a medial portion overlying the silicon substrate and lateral edges on the footings, removing the footings leaving notches at the lateral edges of the polysilicon emitter and refilling the notches with a thin polysilicon film. The bipolar transistor in a BiCMOS integrated circuit resulting from this process includes a silicon semiconductor substrate having a substantially flat surface, a field oxide film laterally bounding the silicon semiconductor substrate and a polysilicon emitter abutting the flat surface of the silicon semiconductor substrate.

Abstract: A process is disclosed for forming an isolation region in a substrate of an integrated circuit structure while minimizing the creation of stress in the substrate which comprises forming a first mask over a portion of the substrate where an isolation region is to be formed, forming an isolation slot in the substrate through an opening in the mask, oxidizing the walls of said isolation slot, removing the first mask, growing an epitaxial layer over the substrate which fills or covers the remainder of the isolation slot, forming a second mask over the epitaxial layer with an oversize opening therein over the isolation slot beneath the epitaxial layer, and oxidizing the exposed portion of the epitaxial layer through the opening in the second mask to form an oxide cap over the isolation slot which extends downwardly through the epitaxial layer to the oxide in the isolation slot.