Abstract: A communication system is provided for transmitting a RF signal, which has a frequency band. The communication system comprises: a sigma delta modulator for modulating the RF signal into a broadband signal wherein the signal to noise ratio of the broadband signal is higher in the frequency band of the RF signal than outside the frequency band of the RF signal; an optical transmitter connected with the sigma delta modulator and with an optical fiber for transmitting the broadband signal over the optical fiber; a photo-detector configured for receiving the broadband signal from the optical fiber and converting it into an electrical signal; an output device and a matching circuit configured for power matching and/or noise matching of the photo-detector, at the frequency band of the RF signal, with the output device.

Abstract: A communication system is provided for transmitting a RF signal, which has a frequency band. The communication system comprises: a sigma delta modulator for modulating the RF signal into a broadband signal wherein the signal to noise ratio of the broadband signal is higher in the frequency band of the RF signal than outside the frequency band of the RF signal; an optical transmitter connected with the sigma delta modulator and with an optical fiber for transmitting the broadband signal over the optical fiber; a photo-detector configured for receiving the broadband signal from the optical fiber and converting it into an electrical signal; an output device and a matching circuit configured for power matching and/or noise matching of the photo-detector, at the frequency band of the RF signal, with the output device.

Abstract: Described herein is a feed forward equalizer that is configured to operate in a normal operational mode and in a test operational mode. The feed forward equalizer has an input port and an output port which are used for the normal operational mode. A test input port and a test output port are provided in the feed forward equalizer, and are used for the test operational mode. Buffers may be provided for matching the impedance of respective ones of the input, output, test input, and test output ports. The feed forward equalizer allows testing during development, and once mounted in an integrated circuit, without interfering with the normal operational mode.

Abstract: Described herein is a multi-level to binary converter in which a cascade of differential limiting amplifiers are utilised for each signal path to provide both increased gain and increased bandwidth without having to trade one off against the other. Where the multi-level data is duobinary, cascaded amplifiers are coupled to a XOR logic gate. In each path, a copy of the duobinary signal is level shifted using an adjustable threshold before amplification in an amplifier. The shifted and amplified signal is then fed to another amplifier where it undergoes the same steps. The outputs from each path are fed to the XOR logic gate to generate the desired binary signal, corresponding to a decoded synchronized NRZ data stream. Such a multi-level to binary converter is capable of performing at data rates of 50 to 80 Gb/s and above, and can easily be integrated within a chip for high-speed electrical backplane communication, optical backplanes or optical fibre links.

Abstract: Described herein is a feed forward equalizer that is configured to operate in a normal operational mode and in a test operational mode. The feed forward equalizer has an input port and an output port which are used for the normal operational mode. A test input port and a test output port are provided in the feed forward equalizer, and are used for the test operational mode. Buffers may be provided for matching the impedance of respective ones of the input, output, test input, and test output ports. The feed forward equalizer allows testing during development, and once mounted in an integrated circuit, without interfering with the normal operational mode.

Abstract: A filter, comprising: two source-follower stages connected in series and in between input nodes and output nodes, wherein inner nodes connect the two stages; and a frequency dependent feedback circuit connected between the input and output nodes, wherein the filter comprises additional frequency dependent feedback circuits connected between input nodes and inner nodes and between output nodes and inner nodes, the additional frequency dependent feedback circuits comprising capacitors.

Abstract: Disclosed is an ESD protection circuit comprising a plurality of bipolar transistors, namely a plurality of ESD current conducting transistors (Q1, Q2, Q4) in a main ESD current conducting path between a first and a second terminal (T1, T2), and further comprises at least one driving transistor (Q3) connected in parallel to at least one of the ESD current conducting transistors (Q1) and provided for conducting a driving current (Ib2) to one or more of the ESD current conducting transistors (Q3) on occurrence of an ESD event.

Abstract: A filter, comprising: two source-follower stages connected in series and in between input nodes and output nodes, wherein inner nodes connect the two stages; and a frequency dependent feedback circuit connected between the input and output nodes, wherein the filter comprises additional frequency dependent feedback circuits connected between input nodes and inner nodes and between output nodes and inner nodes, the additional frequency dependent feedback circuits comprising capacitors.

Abstract: An amplifier circuit is disclosed. In one embodiment, the amplifier circuit includes an input configured to receive an input signal. The amplifier circuit further includes an amplifier connected to the input that is configured to receive the input signal and generate a modulated input signal based on the input signal and one of a first amplification level and a second amplification level. The amplifier comprises a first transistor configured to receive the input signal and a second transistor connected in cascode with the first transistor. The amplifier circuit further includes a switching component configured to switch the amplifier between the first amplification level and the second amplification level. The amplifier circuit still further includes an output connected to the amplifier and configured to output the modulated input signal.

Abstract: The present disclosure provides a system for receiving signals over a power line distribution. Typically, problems of noise and interference are being solved at the receiver side. Systems of the present disclosure, however, are not limited to the receiver-side solution. Systems according to the present disclosure may also be used at the transmitter side. The receiver comprises a high pass filter, a preselect crossover filter, and an analog front-end receiver architecture.

Abstract: Disclosed is an ESD protection circuit comprising a plurality of bipolar transistors, namely a plurality of ESD current conducting transistors (Q1, Q2, Q4) in a main ESD current conducting path between a first and a second terminal (T1, T2), and further comprises at least one driving transistor (Q3) connected in parallel to at least one of the ESD current conducting transistors (Q1) and provided for conducting a driving current (Ib2) to one or more of the ESD current conducting transistors (Q3) on occurrence of an ESD event.

Abstract: A circuit for end-of-burst detection in a portion of a received bit stream is disclosed. The circuit comprises: a first counter for counting the number of bits in the portion, a second counter for counting the number of bit value transitions in the portion, and a circuit for comparing the counted number of bits in the portion and the counted number of bit value transitions therein with preset values, the circuit for comparing is further arranged for generating a signal indicative of end-of-burst detection based on the result of the comparison.

Abstract: Systems and methods for transferring incoming single-ended burst signals of which at least one characteristic varies widely from burst to burst onto a pair of differential lines. The systems comprise an input for receiving an incoming burst signal, a signal adaptation block for adapting said widely varying characteristic and a single-ended-to-differential converter. In a first aspect a reset signal for resetting a settings determination block, which controls the signal adaptation block, is sent backwards over the differential lines, preferably using a common-mode signal. In a second aspect, a status freezing mechanism is employed for freezing the settings of the settings determination block after the end of the preamble of an incoming burst.

Abstract: An amplifier circuit is disclosed. In one embodiment, the amplifier circuit includes an input configured to receive an input signal. The amplifier circuit further includes an amplifier connected to the input that is configured to receive the input signal and generate a modulated input signal based on the input signal and one of a first amplification level and a second amplification level. The amplifier comprises a first transistor configured to receive the input signal and a second transistor connected in cascode with the first transistor. The amplifier circuit further includes a switching component configured to switch the amplifier between the first amplification level and the second amplification level. The amplifier circuit still further includes an output connected to the amplifier and configured to output the modulated input signal.

Abstract: Systems and methods for transferring incoming single-ended burst signals of which at least one characteristic varies widely from burst to burst onto a pair of differential lines. The systems comprise an input for receiving an incoming burst signal, a signal adaptation block for adapting said widely varying characteristic and a single-ended-to-differential converter. In a first aspect a reset signal for resetting a settings determination block, which controls the signal adaptation block, is sent backwards over the differential lines, preferably using a common-mode signal. In a second aspect, a status freezing mechanism is employed for freezing the settings of the settings determination block after the end of the preamble of an incoming burst.

Abstract: A circuit for end-of-burst detection in a portion of a received bit stream is disclosed. The circuit comprises: a first counter for counting the number of bits in the portion, a second counter for counting the number of bit value transitions in the portion, and a circuit for comparing the counted number of bits in the portion and the counted number of bit value transitions therein with preset values, the circuit for comparing is further arranged for generating a signal indicative of end-of-burst detection based on the result of the comparison.

Abstract: Systems and methods for transferring incoming single-ended burst signals of which at least one characteristic varies widely from burst to burst onto a pair of differential lines. The systems comprise an input for receiving an incoming burst signal, a signal adaptation block for adapting said widely varying characteristic and a single-ended-to-differential converter. In a first aspect a reset signal for resetting a settings determination block, which controls the signal adaptation block, is sent backwards over the differential lines, preferably using a common-mode signal. In a second aspect, a status freezing mechanism is employed for freezing the settings of the settings determination block after the end of the preamble of an incoming burst.

Abstract: The present invention is related to a circuit (1) for detecting activity in a burst-mode receiver. The circuit is arranged for receiving an input signal (2) comprising a preamble. The circuit comprises a differentiator (11) for detecting signal transitions in the input signal (2) whereby the preamble comprises information on operating said differentiator (11). In a preferred embodiment, the information is a time constant. The circuit further comprises an integrator (12) arranged for being fed with an output of the differentiator. The resulting signal is compared to a reference (16). If this reference is crossed, activity is detected. In an embodiment a front-end circuit is presented comprising next to a circuit for detecting activity, a reset circuit arranged for resetting the front-end circuit and a clock phase alignment circuit arranged for recovering the phase.

Abstract: The present invention discloses an analogue-to-digital converter comprising at least two voltage comparator devices. Each of the voltage comparator devices comprises a differential structure of transistors and is arranged for being fed with a same input signal and for generating an own internal voltage reference by means of an imbalance in the differential structure, said two internal voltage references being different. Each voltage comparator is arranged for generating an output signal indicative of a bit position of a digital approximation of the input signal.

Abstract: The present disclosure provides a system for receiving signals over a power line distribution. Typically, problems of noise and interference are being solved at the receiver side. Systems of the present disclosure, however, are not limited to the receiver-side solution. Systems according to the present disclosure may also be used at the transmitter side. The receiver comprises a high pass filter, a preselect crossover filter, and an analog front-end receiver architecture.