Abstract: An LDMOS transistor includes a source capacitor structure and a gate-drain shield which can be interconnected whereby the source capacitor can be grounded to provide an RF ground for the shield and whereby the RF shield can have a positive DC voltage bias to enhance laterally diffused drain conductance without increasing doping therein.

Abstract: An LDMOS transistor includes a trench source capacitor structure and a gate-drain shield which can be interconnected whereby the source capacitor can be grounded to provide an RF ground for the shield and whereby the RF shield can have a positive DC voltage bias to enhance laterally diffused drain conductance without increasing doping therein. The trench capacitor structure can include one or more adjacent trenches to increase capacitor plate area.

Abstract: A LDMOS transistor having a gate shield provides reduced drain coupling to the gate shield and source by restricting the thickness of the gate shield and by confining a source contact to the source region without overlap of the gate.

Abstract: Reduced source resistance is realized in a laterally diffused MOS transistor by fabricating the transistor in a P-doped epitaxial layer on an N-doped semiconductor substrate and using a trench contact for ohmically connecting the N-doped source region to the N-doped substrate.

Abstract: An improved laterally diffused MOS (LDMOS) transistor architecture is provided by using a nitride cap on a gate structure and forming a spacer around the gate structure and then self-aligning a source contact and drain contact with a gate by using the same mask for source and drain dopant implantation and for silicide formation with all source and drain areas being silicided. The reduced source/drain on resistance (Rdson), shorter distance from channel to source contact, and better gate oxide integrity improves operating linearity, increases Ft and GM and reduces the drift in Idq and Rdson.

Abstract: In a SOI structure according to the invention, a substrate region directly adjacent and underlying the buried oxide layer is doped with a dopant having a conductivity type opposite that of the substrate. This produces a junction between the doped layer and the substrate. Appropriately biasing this junction creates a depletion layer, which effectively extends the width of the buried oxide layer deep into the substrate, thereby reducing parasitic capacitance in the SOI structure, particularly for inductors, interconnects, and other passive circuit elements. Reducing parasitic capacitance reduces associated substrate losses and RC propagation delays. These benefits become increasingly important at high frequencies encountered in RF wireless communication and high speed digital applications.

Abstract: In a SOI structure according to the invention, a substrate region directly adjacent and underlying the buried oxide layer is doped with a dopant having a conductivity type opposite that of the substrate. This produces a junction between the doped layer and the substrate. Appropriately biasing this junction creates a depletion layer, which effectively extends the width of the buried oxide layer deep into the substrate, thereby reducing parasitic capacitance in the SOI structure, particularly for inductors, interconnects, and other passive circuit elements. Reducing parasitic capacitance reduces associated substrate losses and RC propagation delays. These benefits become increasingly important at high frequencies encountered in RF wireless communication and high speed digital applications.

Abstract: The present method for forming a BICMOS device includes the steps of defining first and second active regions for formation of bipolar and MOS transistors respectively. A gate oxide is provided over the second active region, and a polysilicon layer portion is provided over the gate oxide. A second, relatively thick polysilicon layer is provided over the resulting structure so as to overlie the first and second active regions, gate oxide and polysilicon layer portion. A portion of the thick polysilicon layer overlying the first active region is masked, and the unmasked portion of the thick polysilicon layer is etched to thin it. After removal of the masking, the processing steps to complete the bipolar transistor and MOS transistor are undertaken, the thinning of the unmasked portion of the thick polysilicon layer having been undertaken so that as appropriate etching in further processing takes place, gouging of the first active region during such further etching is avoided.