Patents by Inventor Johan Dick Boter

Johan Dick Boter has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240162314
    Abstract: A multi-time programmable memory cell is provided. The multi-time programmable memory cell includes a floating gate formed on a field oxide region formed on a semiconductor substrate. A control gate is formed on the field oxide region and located parallel to a first portion of the floating gate. A program-erase electrode is formed on the field oxide region and proximate to a second portion of the floating gate. A first well region and a second well region are formed in the semiconductor substrate such that a channel region is formed between the first well region and the second well region with a third portion of the floating gate overlaying the channel region.
    Type: Application
    Filed: November 11, 2022
    Publication date: May 16, 2024
    Inventors: Johan Dick Boter, Jerome Guillaume Anna Dubois, Michiel Jos van Duuren
  • Publication number: 20150102398
    Abstract: Non-volatile floating gate devices and approaches involve setting or maintaining threshold voltage characteristics relative to thermal processing. In connection with various embodiments, a floating gate device includes a polycrystalline silicon material having an impurity therein. The impurity interacts with the polycrystalline material to resist changes in grain size of the polycrystalline silicon material during thermal processing, and setting charge storage characteristics relative to threshold voltages for the floating gate device.
    Type: Application
    Filed: December 18, 2014
    Publication date: April 16, 2015
    Inventors: Henderikus Albert Van der Vegt, Guido Jozef Maria Dormans, Johan Dick Boter, Guoqiao Tao
  • Publication number: 20120043600
    Abstract: Non-volatile floating gate devices and approaches involve setting or maintaining threshold voltage characteristics relative to thermal processing. In connection with various embodiments, a floating gate device includes a polycrystalline silicon material having an impurity therein. The impurity interacts with the polycrystalline material to resist changes in grain size of the polycrystalline silicon material during thermal processing, and setting charge storage characteristics relative to threshold voltages for the floating gate device.
    Type: Application
    Filed: August 18, 2010
    Publication date: February 23, 2012
    Inventors: Henderikus Albert Van der Vegt, Guido Jozef Maria Dormans, Johan Dick Boter, Guoqiao Tao
  • Publication number: 20110298034
    Abstract: A non-volatile memory cell (200) comprising a floating gate transistor (206) comprising a floating gate (10) positioned between a control gate (14) and a first channel region (232) and an access gate transistor (208) comprising an access gate (22) and a second channel region (234), the first channel region (232) comprising a first implant (242) with a first dosage level (234), and the second channel region comprising a second implant (244) having a second dosage level, the first dosage level being less than the second dosage level.
    Type: Application
    Filed: June 2, 2011
    Publication date: December 8, 2011
    Applicant: NXP B.V.
    Inventors: Johan Dick Boter, Guoqiao Tao, Guido Jozef Maria Dormans, Joachim Christoph Hans Garbe