Abstract: The present invention relates to a method of manufacturing a capacitive micro- machined transducer (100), in particular a CMUT, the method comprising depositing a first electrode layer (10) on a substrate (1), depositing a first dielectric film (20) on the first electrode layer (10), depositing a sacrificial layer (30) on the first dielectric film (20), the sacrificial layer (30) being removable for forming a cavity (35) of the transducer, depositing a second dielectric film (40) on the sacrificial layer (30), depositing a second electrode layer (50) on the second dielectric film (40), and patterning at least one of the deposited layers and films (10, 20, 30, 40, 50), wherein the depositing steps are performed by Atomic Layer Deposition. The present invention further relates to a capacitive micro-machined transducer (100), in particular a CMUT, manufactured by such method.

Abstract: The present invention relates to a method of manufacturing a capacitive micro- machined transducer (100), in particular a CMUT, the method comprising depositing a first electrode layer (10) on a substrate (1), depositing a first dielectric film (20) on the first electrode layer (10), depositing a sacrificial layer (30) on the first dielectric film (20), the sacrificial layer (30) being removable for forming a cavity (35) of the transducer, depositing a second dielectric film (40) on the sacrificial layer (30), depositing a second electrode layer (50) on the second dielectric film (40), and patterning at least one of the deposited layers and films (10, 20, 30, 40, 50), wherein the depositing steps are performed by Atomic Layer Deposition. The present invention further relates to a capacitive micro-machined transducer (100), in particular a CMUT, manufactured by such method.

Abstract: The electronic device comprises a network of at least one thin-film capacitor and at least one inductor on a first side of a substrate of a semiconductor material. The substrate has a resistivity sufficiently high to limit electrical losses of the inductor and being provided with an electrically insulating surface layer on its first side. A first and a second lateral pin diode are defined in the substrate, each of the pin diodes having a doped p-region, a doped n-region and an intermediate intrinsic region. The intrinsic region of the first pin diode is larger than that of the second pin diode.

Abstract: A method of providing an electric device with a vertical component and the device itself are disclosed. The electric device may be a transistor device, such as a FET device, with a vertical channel, such as a gate around transistor, or double-gate transistor First an elongate structure, such as a nanowire is provided to a substrate. Subsequently, a first conductive layer separated from the substrate and from the elongate structure by a dielectric layer is provided. Further, a second conductive layer being separated from the first conductive layer by a separation layer is being provided in contact with at least a top section of the elongate structure.

Abstract: A method of making a comparatively small substrate (12) compatible with manufacturing equipment for a larger-size standard substrate is disclosed. The standard substrate (1) has a surface (10) in which a depression (8) is formed, in which depression the small substrate is connected by means of a layer of a bonding material (13). The depression is formed so as to have a flat bottom (9) extending parallel to the surface. The depression has a depth such that, after the small substrate has been connected with its rear side to the bottom of the depression of the standard substrate by means of the layer of bonding material, the front side (14) of the small substrate forms a free surface which practically coincides with the surface (10) of the carrier wafer.

Abstract: The present invention provides a trench isolation structure, comprising a trench groove (4) in a semiconductor slab (1) with a buried layer (2). The trench groove (4) is lined with first insulating material (5), then filled with a first filler material (6) up to the level of the buried layer. Then second insulating material (7), for example an oxide, is preferably applied in the volume which is surrounded by the buried layer (2). The remaining part of the trench groove (4) is either filled with second filler material (8) or with second insulating material. Said structure provides lower capacitive coupling between buried layer (2) edge and substrate (1), with improved thermal behavior.The invention furthermore provides a semiconductor assembly comprising said trench isolation structure and at least one semiconductor device, as well as a method for forming such a trench isolation structure.

Abstract: The invention relates to a radiation-emitting semiconductor device (10) with a semiconductor body (1) and a substrate (2), wherein the semiconductor body (1) comprises a vertical bipolar transistor with an emitter region (3), a base region (4) and a collector region (5), which regions are each provided with a connection region (6, 7, 8), and the border between the base region (4) and the collector region (5) forms a pn-junction and, in operation, at a reverse bias of the pn-junction or at a sufficiently large collector current, avalanche multiplication of charge carriers occurs whereby radiation is generated in the collector region (5). According to the invention, the collector region (5) has a thickness through which transmission of the generated radiation occurs, and the collector region (5) borders on a free surface of the semiconductor body (1).