Patents by Inventor Johan Nijs
Johan Nijs has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6825104Abstract: The present invention describes a method of manufacturing a semiconductor device, comprising a semiconductor substrate in the shape of a slice, the method comprising the steps of: step 1) selectively applying a pattern of a solids-based dopant source to a first major surface of said semiconducting substrate; step 2) diffusing the dopant atoms from said solids-based dopant source into said substrate by a controlled heat treatment step in a gaseous environment surrounding said semi-conducting substrate, the dopant from said solids-based dopant source diffusing directly into said substrate to form a first diffusion region and, at the same time, diffusing said dopant from said solids-based dopant source indirectly via said gaseous environment into said substrate to form a second diffusion region in at least some areas of said substrate to form a second diffusion region in at least some areas of said substrate not covered by said pattern; and step 3) forming a metal contact pattern substantially in alignment withType: GrantFiled: January 27, 2003Date of Patent: November 30, 2004Assignee: Interuniversitair Micro-Elektronica Centrum (IMEC)Inventors: Jörg Horzel, Jozef Szlufcik, Mia Honoré, Johan Nijs
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Patent number: 6815247Abstract: A thin-film opto-electronic device on a conductive silicon-containing substrate includes a sequence of layers. The layers include a layer of a porous medium preferably a porous silicon, on a substrate. The porous layer has both light diffusing and light reflecting properties. In addition, a non-porous layer is located on said porous silicon layer, with at least one first region and at least one second region being in said non-porous layer. The first region is of a first conductivity type acting as a light absorber and the second region has a conductivity of a second type, different from said first conductivity type. The sequence of layers is such that optical confinement is realised in the device.Type: GrantFiled: August 19, 2003Date of Patent: November 9, 2004Assignee: Interuniversitair Microelektronica Centrum (IMEC)Inventors: Lieven Stalmans, Jef Poortmans, Matty Caymax, Khalid Said, Johan Nijs
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Publication number: 20040087056Abstract: A thin-film opto-electronic device on a conductive silicon-containing substrate includes a sequence of layers. The layers include a layer of a porous medium preferably a porous silicon, on a substrate. The porous layer has both light diffusing and light reflecting properties. In addition, a non-porous layer is located on said porous silicon layer, with at least one first region and at least one second region being in said non-porous layer. The first region is of a first conductivity type acting as a light absorber and the second region has a conductivity of a second type, different from said first conductivity type. The sequence of layers is such that optical confinement is realised in the device.Type: ApplicationFiled: August 19, 2003Publication date: May 6, 2004Inventors: Lieven Stalmans, Jef Poortmans, Matty Caymax, Khalid Said, Johan Nijs
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Patent number: 6683367Abstract: The present invention is related to a thin-film opto-electronic device and a method of fabricating the same. Particularly this thin film opto-electronic device is fabricated on a Si-containing substrate. The thin-film material is a crystalline semiconductor material. In order to increase the efficiency of this device a porous silicon layer is applied between the thin-film and the substrate. This porous silicon layer has both light reflecting and light diffusing properties thereby giving rise to light confinement in the thin-film.Type: GrantFiled: April 9, 2001Date of Patent: January 27, 2004Assignee: IMEC vzwInventors: Lieven Stalmans, Jef Poortmans, Matty Caymax, Khalid Said, Johan Nijs
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Publication number: 20030134469Abstract: The present invention describes a method of manufacturing a semiconductor device, comprising a semiconductor substrate in the shape of a slice, the method comprising the steps of: step 1) selectively applying a pattern of a solids-based dopant source to a first major surface of said semiconducting substrate; step 2) diffusing the dopant atoms from said solids-based dopant source into said substrate by a controlled heat treatment step in a gaseous environment surrounding said semi-conducting substrate, the dopant from said solids-based dopant source diffusing directly into said substrate to form a first diffusion region and, at the same time, diffusing said dopant from said solids-based dopant source indirectly via said gaseous environment into said substrate to form a second diffusion region in at least some areas of said substrate to form a second diffusion region in at least some areas of said substrate not covered by said pattern; and step 3) forming a metal contact pattern substantially in alignment withType: ApplicationFiled: January 27, 2003Publication date: July 17, 2003Applicant: IMEC vzw, a research center in the country of BelgiumInventors: Jorg Horzel, Jozef Szlufcik, Mia Honore, Johan Nijs
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Patent number: 6552414Abstract: The present invention describes a method of manufacturing a semiconductor device, comprising a semiconductor substrate (2) in the shape of a slice, the method comprising the steps of: step 1) selectively applying a pattern of a solids-based dopant source to a first major surface of said semiconducting substrate (2); step 2) diffusing the dopant atoms from said solids-based dopant source into said substrate (2) by a controlled heat treatment step in a gaseous environment surrounding said semi-conducting substrate (2), the dopant from said solids-based dopant source diffusing directly into said substrate (2) to form a first diffusion region (12) and, at the time, diffusing said dopant from said solids-based dopant source indirectly via said gaseous environment into said substrate (2) to form a second diffusion region (15) in at least some areas of said substrate (2) not covered by said pattern; and step 3) forming a metal contact pattern (20) substantially in alignment with said first diffusion region (12) withType: GrantFiled: August 27, 1999Date of Patent: April 22, 2003Assignee: IMEC vzwInventors: Jörg Horzel, Jozef Szlufcik, Mia Honoré, Johan Nijs
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Patent number: 6384317Abstract: The solar cell in the semiconductor substrate includes at least a radiation receiving front surface and a second surface. The substrate includes a first region of one type of conductivity and a second region of the opposite conductivity type with at least a first part located adjacent to the front surface and a second part located adjacent to the second surface. The front surface includes conductive contacts to the second region and the second surface has separated contacts to the first region and to the second region. The contacts to the second region at the second surface are connected to the contacts at the front surface through a limited number of vias.Type: GrantFiled: April 3, 2000Date of Patent: May 7, 2002Assignee: IMEC vzwInventors: Emmanuel Van Kerschaver, Jozef Szlufcik, Roland Einhaus, Johan Nijs
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Patent number: 6251756Abstract: An open apparatus is described for the processing of planar thin semiconductor substrates, particularly for the processing of solar cells. The apparatus includes a first zone for the drying and burn-out of organic components from solid or liquid based dopant sources pre-applied to the substrates. The zone is isolated from the remaining zones of the apparatus by an isolating section to prevent cross-contamination between burn-out zone and the remaining processing zones. All the zones of the apparatus may be formed from a quartz tube around which heaters are placed for raising the temperature inside the quartz tube. Each zone may be purged with a suitable mixture of gases, e.g. inert gases such as argon, as well as oxygen and nitrogen. The zones may also be provided with gaseous dopants such as POCl3 and the present invention includes the sequential diffusion of more than one dopant into the substrates. Some of the zones may be used for driving-in the dopants alternatively, for other processes, e.g. oxidation.Type: GrantFiled: July 12, 2000Date of Patent: June 26, 2001Assignee: Interuniversitair Micro-Elektronica Centrum (IMEC vzw)Inventors: Jörg Horzel, Jozef Szlufcik, Johan Nijs
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Patent number: 6117266Abstract: An open apparatus is described for the processing of planar thin semiconductor substrates, particularly for the processing of solar cells. The apparatus includes a first zone for the drying and burn-out of organic components from solid or liquid based dopant sources pre-applied to the substrates. The zone is isolated from the remaining zones of the apparatus by an isolating section to prevent cross-contamination between burn-out zone and the remaining processing zones. All the zones of the apparatus may be formed from a quartz tube around which heaters are placed for raising the temperature inside the quartz tube. Each zone may be purged with a suitable mixture of gases, e.g. inert gases such as argon, as well as oxygen and nitrogen. The zones may also be provided with gaseous dopants such as POCl.sub.3 and the present invention includes the sequential diffusion of more than one dopant into the substrates. Some of the zones may be used for driving-in the dopants alternatively, for other processes, e.g.Type: GrantFiled: April 22, 1998Date of Patent: September 12, 2000Assignee: Interuniversifair Micro-Elektronica Cenirum (IMEC VZW)Inventors: Jorg Horzel, Jozef Szlufcik, Johan Nijs
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Patent number: 5726065Abstract: Method of preparing on a solar cell the top contact pattern which consists of a set of parallel narrow finger lines and wide collector lines deposited essentially at right angles to the finger lines on the semiconductor substrate, characterized in that it comprises at least the following steps:(a) screen printing and drying the set of contact finger lines;(b) printing and drying the wide collector lines on the top of the set of finger lines in a subsequent step;(c) firing both finger lines and collector lines in a single final step in order to form an ohmic contact between the finger lines and the semiconductor substrate and between the finger lines and the wide collector lines.Type: GrantFiled: February 21, 1996Date of Patent: March 10, 1998Assignee: IMEC VZWInventors: Jozef Szlufcik, Johan Nijs, Roland Jozef Fick
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Patent number: 5108936Abstract: A bipolar hetero-junction transistor has an emitter formed which consists of doped and hydrogenated semiconductor material which is at least partly in amorphous form. A high current gain (.beta.) is obtained due to the wide bandgap in the emitter material. Preferably, the layer forming the emitter consists of microcrystalline silicon which is doped and hydrogenated. This yields a small base resistance which is preferable for high frequency purposes. The amorphous bipolar hetero-junction transistor can be produced by a CVD-technique, by using a plasma or by photodissociation. The transistor having a microcrystalline emitter layer can be produced by one of the above methods or by heating an amorphous emitter layer.Type: GrantFiled: May 21, 1991Date of Patent: April 28, 1992Assignee: Interuniveritair Micro Elektronica CentrumInventors: Moustafa Y. Ghannam, Robert Mertens, Johan Nijs
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Patent number: RE37512Abstract: Method of preparing on a solar cell the top contact pattern which consists of a set of parallel narrow finger lines and wide collector lines deposited essentially at right angles to the finger lines on the semiconductor substrate, characterized in that it comprises at least the following steps: (a) screen printing and drying the set of contact finger lines; (b) printing and drying the wide collector lines on the top of the set of finger lines in a subsequent step; (c) firing both finger lines and collector lines in a single final step in order to form an ohmic contact between the finger lines and the semiconductor substrate and between the finger lines and the wide collector lines.Type: GrantFiled: March 10, 2000Date of Patent: January 15, 2002Assignee: Interuniversitair Microelektronica Centrum (IMEC) VZWInventors: Jozef Szlufcik, Johan Nijs, Roland Jozef Fick