Abstract: An information handling system includes a processor, a system baseboard management controller (BMC), and a field-programmable gate array (FPGA) add-in card. The FPGA add-in card includes an FPGA and a card BMC. The FPGA is programmed with a plurality of accelerated function units (AFUs) to perform processing tasks for the processor. The card BMC receives a first indication from the system BMC, the first indication to halt a first processing task associated with a first AFU, halts the first processing task in response to the first indication, receives a second AFU from the system BMC, and reprograms the FPGA with the second AFU.

Abstract: An information handling system includes a processor, a system baseboard management controller (BMC), and a field-programmable gate array (FPGA) add-in card. The FPGA add-in card includes an FPGA programmed with accelerated function units (AFUs) to perform processing tasks for the processor. The AFUs include AFUs of a common type. A card BMC provides a temperature indication to the system BMC. The system BMC determines that a temperature of the FPGA add-in card exceeds a temperature threshold based upon the temperature indication, selects one of the common AFUs to be disabled, and directs the card BMC to disable the selected AFU. The card BMC disables the first AFU and not the second AFU in response to the direction to disable the first AFU.

Abstract: An information handling system includes a controller and first, second and third devices. The devices power-on during a power-on sequence of the information handling system. During the power-on sequence, the controller provides a first power brake signal to the first device via a first power brake line, a second power brake signal to the second device via a second power brake line, and a third power brake signal to the third device via a third power brake line. The controller removes the first power brake signal from the first power brake line. In response to an expiration of a first amount of time, the controller removes the second power brake signal from the second power brake line. In response to an expiration of a second amount of time, the controller removes the third power brake signal from the third power brake line.

Abstract: A first add-in card is connected to a second add-in card via a network communication link using a first network protocol. The first add-in card determines that a first network interface device is directly connected to a second network interface device via the network communication link, and directs that the first and second network interface devices communicate via a second network protocol based upon the first network interface device being directly connected to the second network interface device via the network communication link. The second network protocol transmits a higher proportion of data than the first network protocol.

Abstract: An information handling system includes a device and a baseboard management controller. The device is configured to communicate with a processor of the information handling system. The baseboard management controller is configured to communicate with the device via an in-band communication channel. The baseboard management controller determines whether data is received from the device via an in-band communication channel, and determines whether the baseboard management controller may communicate with the device via an out-of-band communication channel. In response to the data not being received and the baseboard management controller not able to communicate with the device, the baseboard management controller detects a failure of the device. In response to the detection of the failure of the device, the baseboard management controller isolates the device.

Abstract: Embodiments are described for recovery, via a sideband management bus, of firmware of a device such as an FPGA (Field Programmable Gate Array) card installed within an IHS (Information Handling System). A remote access controller of the IHS generates a security key for the device and transmits it to the device. The remote access controller requests the device to report the current version of the firmware in use by the device. The response from the device is authenticated based on the security key. If the current firmware version reported by the device is consistent with the master firmware version, the device is halted and the current firmware of the device is replaced with the master firmware. The device is initialized based on the master firmware used to update the device firmware.

Abstract: Methods, systems, and computer programs encoded on computer storage medium, for receiving a request to switch a mode of an information handling system (IHS) from a multi-socket mode to a multi-single socket mode; in response to receiving the request, placing each socket of the IHS in an auxiliary power state independent of each other; after placing each socket of the IHS in the auxiliary power state, altering parameters of the sockets of the IHS, including: altering CPU straps, power sequencing, reset sequencing, and bus re-direction associated with one or more of the sockets of the IHS; and in response to altering the parameters of the sockets of the IHS, switching the mode of the IHS from the multi-socket mode to the multi-single socket mode such that a processor for each socket is a bootstrap processor.

Abstract: Methods, systems, and computer programs encoded on computer storage medium, for receiving a request to switch a mode of an information handling system (IHS) from a multi-socket mode to a multi-single socket mode; in response to receiving the request, placing each socket of the IHS in an auxiliary power state independent of each other; after placing each socket of the IHS in the auxiliary power state, altering parameters of the sockets of the IHS, including: altering CPU straps, power sequencing, reset sequencing, and bus re-direction associated with one or more of the sockets of the IHS; and in response to altering the parameters of the sockets of the IHS, switching the mode of the IHS from the multi-socket mode to the multi-single socket mode such that a processor for each socket is a bootstrap processor.

Abstract: An information handling system includes a processor, and first and second field-programmable gate array (FPGA) add-in cards. The processor determines a configuration of the information handling system, the configuration defining architectural relationships among the first and second FPGA add-in cards and elements of the information handling system, determines that an accelerated function unit (AFU) performs its associated processing task more efficiently on the first FPGA add-in card than on the second FPGA add-in card based upon the configuration, and programs the first AFU on the first FPGA card in based upon the determination that the first AFU performs its associated processing task more efficiently on the first FPGA add-in card than on the second FPGA add-in card.

Abstract: An information handling system includes a device and a baseboard management controller. The device is configured to communicate with a processor of the information handling system. The baseboard management controller is configured to communicate with the device via an in-band communication channel. The baseboard management controller determines whether data is received from the device via an in-band communication channel, and determines whether the baseboard management controller may communicate with the device via an out-of-band communication channel. In response to the data not being received and the baseboard management controller not able to communicate with the device, the baseboard management controller detects a failure of the device. In response to the detection of the failure of the device, the baseboard management controller isolates the device.

Abstract: An information handling system includes a controller and first, second and third devices. The devices power-on during a power-on sequence of the information handling system. During the power-on sequence, the controller provides a first power brake signal to the first device via a first power brake line, a second power brake signal to the second device via a second power brake line, and a third power brake signal to the third device via a third power brake line. The controller removes the first power brake signal from the first power brake line. In response to an expiration of a first amount of time, the controller removes the second power brake signal from the second power brake line. In response to an expiration of a second amount of time, the controller removes the third power brake signal from the third power brake line.

Abstract: A first add-in card is connected to a second add-in card via a network communication link using a first network protocol. The first add-in card determines that a first network interface device is directly connected to a second network interface device via the network communication link, and directs that the first and second network interface devices communicate via a second network protocol based upon the first network interface device being directly connected to the second network interface device via the network communication link. The second network protocol transmits a higher proportion of data than the first network protocol.

Abstract: An information handling system includes a processor, a system baseboard management controller (BMC), and a field-programmable gate array (FPGA) add-in card. The FPGA add-in card includes an FPGA programmed with accelerated function units (AFUs) to perform processing tasks for the processor. The AFUs include AFUs of a common type. A card BMC provides a temperature indication to the system BMC. The system BMC determines that a temperature of the FPGA add-in card exceeds a temperature threshold based upon the temperature indication, selects one of the common AFUs to be disabled, and directs the card BMC to disable the selected AFU. The card BMC disables the first AFU and not the second AFU in response to the direction to disable the first AFU.

Abstract: An information handling system includes a processor, and first and second field-programmable gate array (FPGA) add-in cards. The processor determines a configuration of the information handling system, the configuration defining architectural relationships among the first and second FPGA add-in cards and elements of the information handling system, determines that an accelerated function unit (AFU) performs its associated processing task more efficiently on the first FPGA add-in card than on the second FPGA add-in card based upon the configuration, and programs the first AFU on the first FPGA card in based upon the determination that the first AFU performs its associated processing task more efficiently on the first FPGA add-in card than on the second FPGA add-in card.

Abstract: An information handling system includes a processor, a system baseboard management controller (BMC), and a field-programmable gate array (FPGA) add-in card. The FPGA add-in card includes an FPGA and a card BMC. The FPGA is programmed with a plurality of accelerated function units (AFUs) to perform processing tasks for the processor. The card BMC receives a first indication from the system BMC, the first indication to halt a first processing task associated with a first AFU, halts the first processing task in response to the first indication, receives a second AFU from the system BMC, and reprograms the FPGA with the second AFU.

Abstract: Embodiments are described for securing access to a debug port of an FPGA (Field Programmable Gate Array) card installed within an IHS (Information Handling System). A remote access controller determines the status of the FPGA card debug port via a query to a management controller of the FPGA card. The remote access controller generates a passcode for the debug port and disables the debug port via a message to the management controller. The management controller detects a request, that includes a requestor password, for access to the debug port. The remote access controller authorizes the requestor's access to the debug port if the requestor password matches the generated passcode. The remote access controller disables the debug port upon each power cycle of the FPGA card or upon detecting removal of a device from the debug port.

Abstract: Embodiments are described for identifying critical sensors of a device, such as a FPGA (Field Programmable Gate Array) card, installed within an IHS (Information Handling System). A remote access controller identifies temperature sensors provided by the device and determine alert level thresholds for each of the sensors. The temperature sensors are ranked based on the respective ranges of the alert level thresholds. A first portion of the temperature sensors with the smallest ranges of alert level thresholds are assigned to a first ranked list. Readings from the temperature sensors are monitored and temperature sensors indicating temperature sensor readings rising faster than a first threshold are assigned to a second ranked list. A portion of the temperature sensors in the first ranked list and a portion of the temperature sensors in the second ranked list are designated for use by an airflow cooling system of the IHS.

Abstract: Periods of interoperability of sideband buses prevent effective management of managed devices by a remote access controller. Embodiments avoid periods of inoperability of sideband buses and recover the sideband bus without resetting the managed devices or the IHS (Information Handling System). The remote access controller configures timer and transmits the timer to a managed device. The managed device monitors the sideband for messages for the remote access controller. If no messages are received before expiration of the timer, the managed device resets its sideband bus endpoint, without resetting the managed device.

Abstract: In accordance with embodiments of the present disclosure, a method may include: (i) retrieving a profile from a management controller of an information handling system, the management controller configured to provide management of the information handling system via management traffic communicated between the management controller and a dedicated management network external to the information handling system, and the profile including data regarding a configuration of the management controller; (ii) comparing the profile to one or more golden profiles to determine whether security of the management controller has been compromised; (iii) responsive to the profile matching a golden profile of the one or more golden profiles, permitting the management controller to continue execution; and (iv) responsive to the profile failing to match a golden profile of the one or more golden profiles, taking remedial action with respect to the management controller.

Abstract: An information handling system and method provides basic input/output system (BIOS) recovery. At a baseboard management controller (BMC), a basic input/output system (BIOS) boot failure is detected. A non-volatile memory device a recovery image is obtained. The recovery image comprises instructions to perform a system software management (SSM) task. The instructions to perform the SSM task are executed. The execution comprises loading a BIOS image from a BMC persistent storage memory device, verifying the BIOS image, and writing the BIOS image to a BIOS non-volatile memory device. The system and method may utilize a recovery flash memory device attached to the BMC, a recovery flash memory device attached to a southbridge portion of a chipset, or a combination thereof to perform the BIOS recovery.