Abstract: A photo-voltaic element comprising a stack of layers is disclosed, as well as a method of making the photo-voltaic element. The stack of layers at least includes the following: a first electrode layer, a first charge carrier transport layer, an insulating layer, a second electrode layer, a second charge carrier transport layer, and a photo-electric conversion layer. The photo-electric conversion layer comprises a plurality of distributed extensions extending through the second charge carrier transport layer, the second electrode layer, and the insulating layer, to the first charge carrier transport layer. The distributed extensions have an effective cross-section Deff in the range of 0.5 to 10 micron, and have an average pitch in the range of 1.1 to 5 times said effective cross-section.

Abstract: A polar transmitter is provided. The polar transmitter includes a baseband generation unit configured to generate phase data bits and amplitude data bits of an output pulse. The polar transmitter further includes a bandwidth control unit downstream to the baseband generation unit configured to regulate the width of the output pulse. Moreover, the polar transmitter includes a pulse shaping unit downstream to the bandwidth control unit configured to generate a predefined amplitude envelope of the output pulse. In this context, the pulse shaping unit includes a delay-line with a plurality of taps, where each tap output is configured to be amplitude weighted in order to generate the amplitude envelope of the output pulse.

Abstract: A wireless communication device with localization capabilities comprises a first receive chain for receiving a first signal from a first static communication node, and at least a second receive chain for receiving at least a second signal from at least a second static communication node. The first and at least one second receive chains are configured to simultaneously receive the first and at least one second signals. The wireless communication device is configured to determine a first distance between the wireless communication device and the first static communication node on the basis of the first signal, determine at least a second distance between the wireless communication device and the at least one second static communication node on the basis of the at least one second signal, and determine a location of the wireless communication device on the basis of the first and least one second distances.

Abstract: The invention relates to a photovoltaic module comprising (a) a front layer (1) arranged on the sunlight facing side of the photovoltaic module, wherein the front layer (1) comprises a first polypropylene composition, comprising a polypropylene, wherein the transmission of the front layer for light in the wavelength range of 350 nm to 1200 nm is on average at least 65% as compared to a situation without the front layer as determined according to ASTM D1003-13, (b) a sealing layer (2,4) which at least partly encapsulates a plurality of photovoltaic cells (3), wherein the sealing layer (2, 4) comprises a polyolefin elastomer composition comprising an ethylene-?-olefin copolymer and (c) a back layer (5), wherein the back layer (5) comprises a first reinforced polypropylene layer comprising a second polypropylene composition comprising a polypropylene and optionally a reinforcing filler, wherein the sealing layer is arranged between the front layer and the back layer.

Abstract: An all-digital phase locked loop (ADPLL) is provided. The ADPLL comprises a pattern generator adapted to generate a frequency control word (FCW) based on a predefined setting and a system clock. In addition, the ADPLL comprises a phase accumulator adapted to translate the FCW into a phase trajectory. The ADPLL further comprises a phase comparator adapted to generate a phase error signal representing a difference between the phase trajectory and the phase of an output oscillation frequency. Moreover, the ADPLL comprises a controller adapted to control a phase of the output oscillation frequency with respect to the phase trajectory.

Abstract: A pre-formed solar panel (1) to be mounted on a support plane (SP) is disclosed. In a direction from a first end (E1) to a second opposing end (E2), the panel has at least a first planar section (S1), a plastically deformed section (P) and a second planar section (S2), wherein the plastically deformed section maintains the first and the second planar section relative to each other at an enclosed angle (A1) in a range between 30° and 170°, and wherein an area of at least one of the planar sections is provided with a photovoltaic layer (3).

Abstract: A circuit for facilitating random edge injection locking of an oscillator comprises a clock signal and a digitally controlled delay line, where the digitally controlled delay line is configured to delay the clock signal, thereby generating a delayed clock signal. The circuit further comprises an edge selector configured to generate a phase select signal with a random pulse sequence. Moreover, the circuit comprises a pulse generator downstream to the digitally controlled delay line configured to generate injection pulses from the delayed clock signal for at least two phases of the oscillator based on the phase select signal.

Abstract: A radio frequency, RF, transmitter, comprises a digitally controlled oscillator, DCO, configured to generate an RF signal; and digital modulation circuitry connected to the DCO for modulation of the RF signal, and driven by an RF clock signal derived from the RF signal, wherein the digital modulation circuitry comprises a module configured to apply a compensation for modulation jitter due to the modulation circuitry being driven by the RF clock signal and a compensation for DCO non-linearity.

Abstract: A polar transmitter is provided. The polar transmitter includes a baseband generation unit configured to generate phase data bits and amplitude data bits of an output pulse. The polar transmitter further includes a bandwidth control unit downstream to the baseband generation unit configured to regulate the width of the output pulse. Moreover, the polar transmitter includes a pulse shaping unit downstream to the bandwidth control unit configured to generate a predefined amplitude envelope of the output pulse. In this context, the pulse shaping unit includes a delay-line with a plurality of taps, where each tap output is configured to be amplitude weighted in order to generate the amplitude envelope of the output pulse.

Abstract: A circuit for facilitating random edge injection locking of an oscillator comprises a clock signal and a digitally controlled delay line, where the digitally controlled delay line is configured to delay the clock signal, thereby generating a delayed clock signal. The circuit further comprises an edge selector configured to generate a phase select signal with a random pulse sequence. Moreover, the circuit comprises a pulse generator downstream to the digitally controlled delay line configured to generate injection pulses from the delayed clock signal for at least two phases of the oscillator based on the phase select signal.

Abstract: The present disclosure concerns a photovoltaic sandwich panel (1) comprising a photovoltaic element layer (2) provided between a protective front layer (3), and a fiber reinforced back layer (4), wherein: the protective front layer is formed from a compound comprising a first thermoplastic polymer (PI); and the fiber reinforced back layer comprises a second thermoplastic polymer (P2) with a fibrous filler material (F). The disclosure further concerns a method for manufacturing a photovoltaic sandwich panel and an assembly of said panels.

Abstract: A signal generator has a nominal frequency control input and a modulation frequency control input and comprises an oscillator, with a first set of capacitors at least partially switchably connectable for adjusting a frequency of the oscillator as part of a phase-locked loop, and a second set of capacitors comprised in a modulation stage of the oscillator, switchably connectable for modulating the frequency and controlled by the modulation frequency control input; a modulation gain estimation stage configured to determine a frequency-to-capacitor modulation gain; and a modulation range reduction module configured for clipping a modulation range of the oscillator to a range achievable using the second set of capacitors, using the modulation gain averaging out, in time, a phase error caused by the said clipping; and mimicking the said clipping, additively output to the nominal frequency control input to compensate said PLL for the said modulation.

Abstract: An all-digital phase locked loop (ADPLL) is provided. The ADPLL comprises a pattern generator adapted to generate a frequency control word (FCW) based on a predefined setting and a system clock. In addition, the ADPLL comprises a phase accumulator adapted to translate the FCW into a phase trajectory. The ADPLL further comprises a phase comparator adapted to generate a phase error signal representing a difference between the phase trajectory and the phase of an output oscillation frequency. Moreover, the ADPLL comprises a controller adapted to control a phase of the output oscillation frequency with respect to the phase trajectory.

Abstract: A signal generator has a nominal frequency control input and a modulation frequency control input and comprises an oscillator, with a first set of capacitors at least partially switchably connectable for adjusting a frequency of the oscillator as part of a phase-locked loop, and a second set of capacitors comprised in a modulation stage of the oscillator, switchably connectable for modulating the frequency and controlled by the modulation frequency control input; a modulation gain estimation stage configured to determine a frequency-to-capacitor modulation gain; and a modulation range reduction module configured for clipping a modulation range of the oscillator to a range achievable using the second set of capacitors, using the modulation gain averaging out, in time, a phase error caused by the said clipping; and mimicking the said clipping, additively output to the nominal frequency control input to compensate said PLL for the said modulation.

Abstract: A radio frequency, RF, transmitter, comprises a digitally controlled oscillator, DCO, configured to generate an RF signal; and digital modulation circuitry connected to the DCO for modulation of the RF signal, and driven by an RF clock signal derived from the RF signal, wherein the digital modulation circuitry comprises a module configured to apply a compensation for modulation jitter due to the modulation circuitry being driven by the RF clock signal and a compensation for DCO non-linearity

Abstract: A signal generator comprises (i) a first set of capacitors at least partially switchably connectable for adjusting a frequency of an oscillator as part of a phase-locked loop and (ii) a second set of capacitors comprised in one or more oscillator control subsystems. A method of controlling the signal generator comprises: (i) acquiring a frequency lock in the phase-locked loop, (ii) calculating, in conjunction with the acquiring of the frequency lock, a systematic capacitance error of the first set of capacitors due to process, voltage, and temperature variations based on the frequency of the oscillator and a switching state of the first set of capacitors, and (iii) calibrating the one or more oscillator control subsystems using the systematic capacitance error, thereby compensating for process, voltage, and temperature variations common between the first set of capacitors and the second set of capacitors.

Abstract: A photo-voltaic element (1) comprising a stack of layers is provided. The stack of layers at least includes the following layers arranged in the order named: a first electrode layer, a first charge carrier transport layer, an insulating layer, a second electrode layer, a second charge carrier transport layer, and a photo-electric conversion layer. The photo-electric conversion layer (70), comprises a plurality of distributed extensions (72) extending through the second charge carrier transport layer (60), the second electrode layer (50) and the insulating layer (40) to the first charge carrier transport layer (30). The extensions (72) have an effective cross-section Deff in the range of 0.5 to 10 micron, and have an average pitch in the range of 1.1 to 5 times said effective cross-section.

Abstract: A signal generator comprises (i) a first set of capacitors at least partially switchably connectable for adjusting a frequency of an oscillator as part of a phase-locked loop and (ii) a second set of capacitors comprised in one or more oscillator control subsystems. A method of controlling the signal generator comprises: (i) acquiring a frequency lock in the phase-locked loop, (ii) calculating, in conjunction with the acquiring of the frequency lock, a systematic capacitance error of the first set of capacitors due to process, voltage, and temperature variations based on the frequency of the oscillator and a switching state of the first set of capacitors, and (iii) calibrating the one or more oscillator control subsystems using the systematic capacitance error, thereby compensating for process, voltage, and temperature variations common between the first set of capacitors and the second set of capacitors.

Abstract: The present disclosure relates to a Digital Phase Locked Loop (DPLL) for phase locking an output signal to a reference clock signal. The DPLL comprises a phase detector for detecting a phase error of a feedback signal with respect to the reference clock signal. The DPLL comprises a digitally controlled oscillator for generating the output signal based at least on a frequency control word and at least one control signal representative of the phase error. The phase detector comprises an integer circuit for generating a first control signal representative of an integer phase error. The phase detector comprises a fractional circuit comprising a Time-to-Digital Converter (TDC) for processing the feedback signal and a delayed reference clock signal. The fractional circuit is provided for generating from the TDC output a second control signal representative of a fractional phase error. The DPLL comprises an unwrapping unit for unwrapping the TDC output.

Abstract: Embodiments described herein include a receiver, a method, and a plurality of high-pass filters for demodulating a radio frequency (RF) signal. An example receiver includes a plurality of high-pass filters. The receiver includes a demodulator configured to demodulate an RF signal received at an input of the demodulator and configured to output a demodulated signal. The receiver also includes a plurality of high-pass filters connected to an output of the demodulator. The plurality of high-pass filters are configured to receive the demodulated signal and configured to high-pass filter the demodulated signal. The plurality of high-pass filters are configured to operate with a first set of filter responses during a first time period of the demodulated signal and configured to operate with a second set of filter responses during a second time period of the demodulated signal.