Patents by Inventor Johan Vertommen

Johan Vertommen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250125291
    Abstract: A semiconductor product is provided. The semiconductor product comprises a first wafer (21) comprising a first active pad array (21a), and at least a second wafer (22) comprising at least a second active pad array (22a). In this context, the first wafer (21) and the at least one second wafer (22) are bonded together. In addition to this, the first wafer (21) and/or the at least one second wafer (22) comprises a transition area (23) being directly adjacent to the first active pad array (21a) and/or the at least one second active pad array (22a).
    Type: Application
    Filed: February 21, 2023
    Publication date: April 17, 2025
    Inventors: Emmanuel LE BOULBAR, Soeren STEUDEL, Johan VERTOMMEN, Robert MILLER, Joeri DE VOS, Stefaan VAN HUYLENBROECK, Eric BEYNE, Liesbeth WITTERS
  • Publication number: 20250113663
    Abstract: A method (100) is provided for making light emitting mesa structures on a semiconductor wafer, each mesa structure comprising a first doped layer, a second doped layer, and an emission layer in-between. The method comprises the steps of providing (101) a first mask for assigning a shape of a sidewall of the mesa structures, etching (102) from the first doped layer according to the first mask up to the emission layer, providing (103) a second mask for assigning a shape of a trench between two adjacent mesa structures, and etching (104) the trench through the emission layer according to the second mask. In this regard, the trench is nonadjacent to the sidewall of the mesa structures.
    Type: Application
    Filed: March 20, 2023
    Publication date: April 3, 2025
    Inventors: Johan VERTOMMEN, Soeren STEUDEL, Emmanuel LE BOULBAR
  • Publication number: 20240413131
    Abstract: A polychrome wafer structure (100,200,200?) comprising a plurality of structured first epitaxial dies (102) having first light-emitting devices (107) configured to emit light of a first color, at least a plurality f structured second epitaxial dies (103) having second light-emitting devices (107?) configured to emit light of a second color. The plurality of the structured first epitaxial dies (102) and the plurality of the structured second epitaxial dies (103) are bonded on a target wafer (507) with a plurality of common monolithic integrated circuits in a manner that the at least one first die and the at least one second die is connected to common monolithic integrated (101) one circuit for simultaneously driving at least one first epitxial die (102) having light-emitting device (107) and at least one second epitaxial die (103) having light-emitting device (107?) by the respective one common monolithic integrated circuit (101).
    Type: Application
    Filed: March 20, 2023
    Publication date: December 12, 2024
    Inventors: Johan VERTOMMEN, Soeren STEUDEL
  • Publication number: 20240363416
    Abstract: A method (100) and a semiconductor structure are provided. The method comprises the steps of providing (101) a semiconductor structure comprising at least one epitaxial layer, and a substrate having a first thickness, removing (102) the at least one epitaxial layer from the substrate in a predefined pattern to form a plurality of epitaxial isles on the substrate, and thinning (103) the substrate from a surface opposite to the plurality of epitaxial isles to a second thickness.
    Type: Application
    Filed: March 29, 2024
    Publication date: October 31, 2024
    Inventors: Soeren STEUDEL, Johan VERTOMMEN
  • Publication number: 20220413289
    Abstract: A display system includes a first die configured to emit light of a first color, a second die configured to emit light of a second color and a third die configured to emit light of a third color. The display system also includes a lens system and an optical waveguide system. The optical waveguide system includes a first grating portion configured to couple in an incident light to the optical waveguide and a second grating portion configured to couple out a transmitting light from the optical waveguide. The first die, the second die and the third die are contained in one package. The lens system is arranged between the package and the optical waveguide system, and is configured to collimate the light of the first color, the light of the second color and the light of the third color onto the first grating portion of the optical waveguide system.
    Type: Application
    Filed: February 17, 2021
    Publication date: December 29, 2022
    Inventors: Alexander MITYASHIN, Soeren STEUDEL, Johan VERTOMMEN
  • Publication number: 20220189830
    Abstract: A method is provided to produce dies for a wafer reconstitution. The method comprises steps of inspecting an epitaxial wafer to detect one or more defects, overlaying a dicing scheme on the epitaxial wafer with the detected defects, classifying the dies in the dicing scheme as good dies or bad dies, and dicing the good dies and transferring the good dies onto a carrier wafer or a target wafer to wafer reconstitution.
    Type: Application
    Filed: December 14, 2021
    Publication date: June 16, 2022
    Inventors: Eric BEYNE, Robert MILLER, Kenneth June REBIBIS, Soeren STEUDEL, Johan VERTOMMEN
  • Patent number: 8747960
    Abstract: The embodiments fill the need to enhance electro-migration performance, provide lower metal resistivity, and improve silicon-to-metal interfacial adhesion for copper interconnects by providing improved processes and systems that produce a silicon-to-metal interface. An exemplary method of preparing a substrate surface of a substrate to selectively deposit a layer of a metal on a silicon or polysilicon surface of the substrate to form a metal silicide in an integrated system is provided.
    Type: Grant
    Filed: August 30, 2006
    Date of Patent: June 10, 2014
    Assignee: Lam Research Corporation
    Inventors: Yezdi Dordi, John Boyd, Tiruchirapalli Arunagiri, Johan Vertommen, Fritz C. Redeker, William Thie, Arthur M. Howald
  • Publication number: 20070292615
    Abstract: The embodiments fill the need to enhance electro-migration performance, provide lower metal resistivity, and improve silicon-to-metal interfacial adhesion for copper interconnects by providing improved processes and systems that produce a silicon-to-metal interface. An exemplary method of preparing a substrate surface of a substrate to selectively deposit a layer of a metal on a silicon or polysilicon surface of the substrate to form a metal silicide in an integrated system is provided.
    Type: Application
    Filed: August 30, 2006
    Publication date: December 20, 2007
    Applicant: Lam Research Corporation
    Inventors: Yezdi Dordi, John Boyd, Tiruchirapalli Arunagiri, Johan Vertommen, Fritz C. Redeker, William Thie, Arthur M. Howald